High-reliability non-volatile memory using a voting mechanism
A memory system includes a processing device (e.g., a controller implemented using a CPU, FPGA, and/or logic circuitry) and memory regions (e.g., in a flash memory or other non-volatile memory) storing data. The processing device receives an access request from a host system that is requesting to read the stored data. In one approach, the memory system is configured to: receive, from the host system over a bus, a read command to access data associated with an address in a non-volatile memory; in response to receiving the read command, access, by the processing device, multiple copies of data stored in at least one memory region of the non-volatile memory; match, by the processing device, data from the copies with each other; select, based on matching data from the copies with each other, first data from a first copy of the copies; and provide, to the host system over the bus, the first data as output data.
1. A system comprising:
a communication interface configured to receive a request containing a logic address from a host system, and provide an output code with multiple data bits from the logic address to the host system in response to the request;
a non-volatile memory configured to store three or more copies of the code;
a flash translation layer mapping the logic address to three or more physical addresses; and
a majority voter configured to, in response to receiving the request, access the three or more copies of the code at the three or more physical addresses, respectively, in parallel, and select one of the copies as the output code based on the one of the copies matching at least one other copy of the copies of the code.
2. The system of claim 1 , further comprising a cache configured to receive the copies of the code accessed by the majority voter.
3. The system of claim 2 , wherein the majority voter is further configured to read data from the copies in the cache to perform an evaluation of the copies to select the one of the copies as the output code.
4. The system of claim 1 , wherein the majority voter selects the one of the copies based on matching code from the copies with each other.
5. The system of claim 4 , wherein the request is a read command.
6. The system of claim 1 , further comprising a boot partition, wherein the request from the host system is a request for data stored in the boot partition.
7. The system of claim 1 , wherein the majority voter is further configured to vary a number of the copies accessed.
8. The system of claim 7 , wherein the number of copies accessed is determined based on at least one memory region of the non-volatile memory from which the copies are accessed.
9. The system of claim 1 , wherein each of the copies is associated with a code stored in the non-volatile memory.
10. The system of claim 9 , wherein the majority voter is further configured to select the one of the copies as the output code by comparing a hash of each of the copies to its respective code.
11. The system of claim 1 , wherein the communication interface is further configured to receive data from the host system that indicates at least one memory region of the non-volatile memory from which to access the copies.
12. The system of claim 1 , wherein the host system sends the request in response to detecting an impending loss of power from a power source.
13. A method comprising:
receiving a request containing a logic address from a host system for a code with multiple data bits stored in a memory;
mapping the logic address to three or more physical addresses in the memory;
in response to receiving the request, accessing three or more copies of the code at the three or more physical addresses, respectively, in parallel in the memory;
performing, by a majority voter of the memory, an evaluation of the accessed copies;
selecting, based on the evaluation, one of the copies as an output code, wherein the one of the copies is selected based on the one of the copies matching at least one other copy of the copies of the code; and
providing the output code to the host system.
14. The method of claim 13 , wherein performing the evaluation comprises matching code from the copies with each other.
15. The method of claim 14 , wherein matching code from the copies with each other comprises matching each of a series of corresponding entries read from each of the copies.
16. The method of claim 13 , wherein each of the copies of the code is stored in a different memory region of the memory.
17. The method of claim 13 , wherein the majority voter determines that a majority of a total number of the accessed copies match each other.
18. The method of claim 13 , wherein the mapping is performed by a flash translation layer of the memory.
19. A non-transitory computer-readable storage medium storing instructions that, when executed by at least one processing device, cause the at least one processing device to perform a method, the method comprising:
receiving a request for a code with multiple data bits stored in a memory, the request containing a logic address for the code;
mapping the logic address to three or more physical addresses of the memory by a flash translation layer;
in response to receiving the request, accessing three or more copies of the code at the three or more physical addresses, respectively, in parallel in the memory;
performing, by a majority voter, an evaluation of the accessed copies;
selecting, based on the evaluation, one of the copies as output code, wherein the one of the copies is selected based on the one of the copies matching at least one other copy of the copies of the code; and
providing the output code as a reply to the request.