Word line booster circuit and method
View Patent ↗A memory circuit includes a plurality of word lines, a word line driver coupled to the plurality of word lines, and a booster circuit coupled to the plurality of word lines. The word line driver is configured to output a first word line signal on a first word line of the plurality of word lines, and the booster circuit includes a first node configured to carry a first power supply voltage and is configured to couple the first word line of the plurality of word lines to the first node responsive to a pulse signal and the first word line signal.
1. A memory circuit comprising:
a plurality of word lines;
a word line driver coupled to the plurality of word lines and configured to output a first word line signal on a first word line of the plurality of word lines; and
a booster circuit comprising:
a first node configured to carry a first power supply voltage, and
a first transistor coupled to the first node,
wherein
the booster circuit is coupled to the plurality of word lines, and
the first transistor is configured to selectively couple the first word line of the plurality of word lines to the first node responsive to a pulse signal and the first word line signal.
2. The memory circuit of claim 1 , wherein
the first word line signal is one word line signal of a plurality of word line signals configured to activate corresponding word lines of the plurality of word lines,
the word line driver is configured to generate the plurality of word line signals based on a plurality of row decode signals, and
the memory circuit further comprises:
a local control circuit configured to generate the plurality of row decode signals; and
a local input output (I/O) circuit configured to generate the pulse signal corresponding to the word line driver activating any word line of the plurality of word lines.
3. The memory circuit of claim 2 , wherein a total number of word line signals of the plurality of word line signals corresponding to the pulse signal is equal to four.
4. The memory circuit of claim 1 , wherein
the booster circuit further comprises a NAND gate,
the first transistor is configured to couple the first word line to the first node responsive to a first signal, and
the NAND gate is configured to generate the first signal responsive to the first word line signal and the pulse signal.
5. The memory circuit of claim 4 , wherein the booster circuit further comprises:
a second node configured to carry a second power supply voltage; and
a second transistor configured to couple the first node to the second node responsive to a power management signal.
6. The memory circuit of claim 1 , wherein
the first word line signal is one word line signal of a plurality of word line signals configured to activate corresponding word lines of the plurality of word lines, and
the booster circuit is configured to couple each word line of the plurality of word lines to the first node responsive to the pulse signal and the corresponding word line signal.
7. The memory circuit of claim 1 , wherein the booster circuit further comprises:
a reference node configured to carry a reference voltage; and
a second transistor configured to couple the first word line to the reference node responsive to a signal complementary to the pulse signal.
8. The memory circuit of claim 1 , wherein
the word line driver is positioned at a first end of each word line of the plurality of word lines, and
the booster circuit is positioned at a second end of each word line of the plurality of word lines, the second end being opposite the first end.
9. The memory circuit of claim 8 , wherein
the plurality of word lines is a first plurality of word lines, and
the memory circuit comprises a second plurality of word lines coupled to the word line driver and the booster circuit and positioned between the word line driver and the booster circuit.
10. The memory circuit of claim 1 , wherein an entirety of each word line of the plurality of word lines is positioned within a single metal layer of the memory circuit.
11. A method of transferring data in a memory circuit, the method comprising:
generating a set of row decode signals and a pulse signal using a control circuit;
based on the set of row decode signals, using a word line driver to activate a first end of a word line;
based on the pulse signal, using a booster circuit to activate a second end of the word line; and
after the activating the first and second ends of the word line, performing a read or write operation on a memory cell coupled to the word line.
12. The method of claim 11 , wherein the using the booster circuit to activate the second end of the word line comprises coupling the word line to a first node configured to carry a first power supply voltage.
13. The method of claim 12 , wherein the coupling the word line to the first node is in response to a boost signal generated in response to the pulse signal and the activating the first end of the word line.
14. The method of claim 12 , further comprising coupling the first node to a second node configured to carry a second power supply voltage in response to a power management signal.
15. The method of claim 11 , wherein the activating the first and second ends of the word line comprises generating a voltage on a single metal layer of the memory circuit.
16. The method of claim 11 , further comprising using the booster circuit to deactivate the second end of the word line based on a signal complementary to the pulse signal.
17. A memory circuit comprising:
a first plurality of word lines;
a word line driver coupled to the first plurality of word lines and positioned at a first end of the first plurality of word lines; and
a first booster circuit coupled to the first plurality of word lines and positioned at a second end of the first plurality of word lines opposite the first end,
wherein
the word line driver is configured to activate each word line of the first plurality of word lines responsive to a corresponding signal of a plurality of signals, and
the first booster circuit is configured to activate each word line of the first plurality of word lines responsive to the corresponding signal of the plurality of signals.
18. The memory circuit of claim 17 , wherein the word line driver is configured to generate the plurality of signals.
19. The memory circuit of claim 17 , wherein each of the word line driver and the booster circuit comprises a plurality of inverters configured to receive the corresponding plurality of signals and active the corresponding first plurality of word lines responsive to the plurality of signals.
20. The memory circuit of claim 17 , further comprising:
a second plurality of word lines, wherein the word line driver is coupled to the second plurality of word lines and positioned at a first end of the second plurality of word lines; and
a second booster circuit coupled to the second plurality of word lines and positioned at a second end of the second plurality of word lines opposite the first end.