Fully self-aligned via with selective bilayer dielectric regrowth

1. A semiconductor device, comprising:

a plurality of conductive structures formed in a first dielectric layer, top surfaces of the plurality of the conductive structures and a top surface of the first dielectric layer being co-planar;

a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls;

a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer so that the sidewalls of the conductive cap layer are surrounded by the second dielectric layer and the top surface of the conductive cap layer is uncovered by the second dielectric layer;

a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer so that the top surface of the conductive cap layer is lower than a top surface of the third dielectric layer and uncovered by the third dielectric layer;

a fourth dielectric layer arranged over the plurality of conductive structures and the third dielectric layer; and

an inverted rectangular stair-shaped interconnect structure formed in the fourth dielectric layer, the inverted rectangular stair-shaped interconnect structure including a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure, the via structure having a first portion that has a first tread positioned over the conductive cap layer and a first riser being perpendicular to the first tread and surrounded by the third dielectric layer, and a second portion that has a second tread disposed over the third dielectric layer and a second riser being perpendicular to the second tread and surrounded by the fourth dielectric layer.

2. The semiconductor device of claim 1 , wherein the second portion of the via structure is disposed between the trench structure and the first portion of the via structure, and has a larger critical dimension than the first portion of the via structure so as to reduce a via resistance of the via structure.

3. The semiconductor device of claim 1 , wherein the first portion of the via structure is electrically coupled to the one of the plurality of conductive structures.

4. The semiconductor device of claim 1 , wherein the conductive cap layer comprises at least one of ruthenium, tungsten, nickel, or cobalt.

5. The semiconductor device of claim 1 , wherein a height of the second dielectric layer is at least twice as great as a height of the third dielectric layer.

6. The semiconductor device of claim 1 , wherein the third dielectric layer is made of metal-containing dielectric material.

7. The semiconductor device of claim 2 , wherein the critical dimensions of the first portion and the second portion are constant.

8. The semiconductor device of claim 1 , wherein the second dielectric layer and the third dielectric layer have different etch resistivities.

9. A semiconductor device, comprising:

a first conductive structure formed in a first dielectric layer, the first conductive structure extending into the first dielectric layer from a top surface of the first dielectric layer;

a conductive cap layer selectively disposed over the first conductive structure and the first dielectric layer with a top surface and sidewalls;

a dielectric stack selectively disposed over the first dielectric layer and arranged between the sidewalls of the conductive cap layer, the sidewalls of the conductive cap layer being surrounded by the dielectric stack, a top surface of the dielectric stack being higher than the top surface of the conductive cap layer, the top surface of the conductive cap layer being uncovered by the dielectric stack; and

an inverted rectangular stair-shaped second conductive structure formed over the first conductive structure, the inverted rectangular stair-shaped second conductive structure having a trench portion and a via portion that is positioned below and coupled to the trench portion, the via portion including a first portion that has a first tread positioned over the conductive cap layer and a first riser being perpendicular to the first tread and surrounded by a first portion of the dielectric stack, a top surface of the first portion of the dielectric stack being co-planer with a top surface of the first portion of the via portion, and a second portion that has a second tread disposed over the first portion of the dielectric stack and a second riser being perpendicular to the second tread and surrounded by a second portion of the dielectric stack that is positioned over the first portion of the dielectric stack, the second portion of the second conductive structure having a larger critical dimension than the first portion of the second conductive structure so as to reduce a resistance of the second conductive structure.

10. The semiconductor device of claim 9 , wherein the dielectric stack comprises a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer positioned over the second dielectric layer.

11. The semiconductor device of claim 10 , wherein a height of the second dielectric layer is at least twice as great as a height of the third dielectric layer.

12. The semiconductor device of claim 9 , wherein the critical dimensions of the first portion and the second portion are constant.