Packaged semiconductor devices having spacer chips with protective groove patterns therein
A packaged integrated circuit device includes a substrate having a spacer chip thereon, which is devoid of active integrated circuits therein but which has a stress-relieving pattern of grooves in an upper surface thereof. A first semiconductor chip is provided, which is bonded to the upper surface of the spacer chip. A molded region is provided, which includes a passivating resin that: (i) at least partially surrounds the first semiconductor chip and the spacer chip, and (ii) extends into at least a portion of the grooves within the upper surface of the spacer chip.
1. A semiconductor package comprising:
a substrate having a lower semiconductor chip and at least a first spacer chip thereon, said first spacer chip having a stress-relieving groove pattern on an upper surface thereof;
an upper semiconductor chip extending on the lower semiconductor chip and on the first spacer chip, said upper semiconductor chip covering at least a portion of an upper surface of the lower semiconductor chip and at least a portion of the upper surface of the first spacer chip containing at least a portion of the groove pattern therein;
an electrically nonconductive adhesive layer, which bonds a lower surface of the upper semiconductor chip to the lower semiconductor chip and to the first spacer chip; and
a mold region, which at least partially surrounds the lower and upper semiconductor chips and the first spacer chip and extends at least partially into the groove pattern.
2. The semiconductor package of claim 1 , wherein the groove pattern includes a plurality of grooves arranged in a grid shape; and wherein the mold region contacts the electrically nonconductive adhesive layer.
3. The semiconductor package of claim 2 , wherein the plurality of grooves include at least some grooves that extend to edges of the upper surface of the first spacer chip.
4. The semiconductor package of claim 1 , wherein the groove pattern includes a groove extending along at least one edge of the upper surface of a first spacer chip.
5. The semiconductor package of claim 1 , wherein the groove pattern includes a plurality of grooves, which are spaced apart from respective edges of the upper surface of the first spacer chip.
6. The semiconductor package of claim 1 , wherein at least a portion of the mold region extends and fills a space between the lower semiconductor chip, the first spacer chip, and the upper semiconductor chip.
7. The semiconductor package of claim 1 , wherein a width of a groove within the groove pattern is within a range from 15 μm to 30 μm.
8. The semiconductor package of claim 1 , wherein a depth of a groove within the groove pattern is within a range from 0.5 μm to 3 μm.
9. The semiconductor package of claim 1 , wherein the at least a first spacer chip includes first and second spacer chips of different size.
10. The semiconductor package of claim 9 , wherein the first and second spacer chips extend opposite first and second sides of the lower semiconductor chip.
11. The semiconductor package of claim 1 , wherein the at least a first spacer chip comprises first through fourth spacer chips which extend opposite first through fourth sides of the lower semiconductor chip, respectively.
12. The semiconductor package of claim 1 , further comprising a second lower semiconductor chip on the substrate; and wherein the first spacer chip extends between the second lower semiconductor chip and the lower surface of the upper semiconductor chip.
13. The semiconductor package of claim 1 , further comprising at least one bonding wire extending between the substrate and the lower semiconductor chip.
14. The semiconductor package of claim 1 , wherein the lower semiconductor chip is a processor chip, and the upper semiconductor chip is a memory chip.
15. The semiconductor package of claim 1 , further comprising a second lower semiconductor chip extending between the first spacer chip and the substrate.
16. A semiconductor package, comprising:
a substrate;
a lower semiconductor chip on the substrate;
a plurality of spacer chips having respective upper surfaces thereon, which contain a grid pattern of grooves therein;
an upper semiconductor chip on the lower semiconductor chip and on the upper surfaces of the plurality of spacer chips;
an electrically nonconductive adhesive layer, which is bonded between a lower surface of the upper semiconductor chip and an upper surface of the lower semiconductor chip and between the lower surface of the upper semiconductor chip and the upper surfaces of the plurality of spacer chips; and
a mold region at least partially surrounding the lower and upper semiconductor chips and the plurality of spacer chips, and at least partially filling a space between the lower semiconductor chip and the plurality of spacer chips, which is covered by the upper semiconductor chip, and at least partially extending into a portion of the grid pattern of grooves.
17. The semiconductor package of claim 16 , wherein the grooves in the upper surfaces of the plurality of spacer chips extend to corresponding edges of the upper surfaces of the plurality of spacer chips.
18. The semiconductor package of claim 16 , wherein the grooves have a width in a range from 15 μm to 30 μm and a depth within a range from 0.5 μm to 3 μm; and wherein a spacing between the plurality of grooves is at least 1.5 times a width of each of the grooves, and is within a range from 20 μm to 100 μm.