IP Library Granted Patent US 11,705,442
Granted Patent B2
US 11,705,442 · App. 17/191,573 · Granted Jul 18, 2023

Semiconductor device

Inventors: Atsushi Hosokawa (Yokohama Kanagawa, JP); Yasuhisa Shintoku (Fujisawa Kanagawa, JP); Yasukazu Noine (Chigasaki Kanagawa, JP); Yoshiharu Katayama (Oita Oita, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L25/16H01L23/49589H01L23/645H01L25/18H01L23/3107H01L24/16H01L24/48H01L24/73H01L2224/16145H01L2224/16265H01L2224/48245H01L2224/48265H01L2224/73207H01L2924/19041H01L2924/19042H01L2924/19104H01L2924/19105
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Quick Facts
Patent No.
US 11,705,442
App. No.
17/191,573
Granted
Jul 18, 2023
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes an integrated circuit (IC) chip and a silicon capacitor. The IC chip has a first terminal and a second terminal on a first surface. The silicon capacitor has a first electrode and a second electrode on a second surface facing the first surface. The first electrode is electrically connected to the first terminal through a first conductive member, and the second electrode is electrically connected to the second terminal through a second conductive member.

Claims (49)

1. A semiconductor device, comprising:

an integrated circuit (IC) chip having a first terminal and a second terminal on a first surface of the IC chip;

a first silicon capacitor on the first surface, the first silicon capacitor having a first electrode and a second electrode on a second surface of the first silicon capacitor that faces the first surface of the IC chip, the first electrode being electrically connected to the first terminal through a first conductive member, and the second electrode being electrically connected to the second terminal through a second conductive member, wherein

a third terminal is on the first surface of the IC chip,

the second terminal is between the first terminal and the third terminal,

the first electrode includes a first portion and a second portion, the first portion being electrically connected to the first terminal through the first conductive member, and the second portion being electrically connected to the third terminal through a third conductive member, and

the second electrode includes a third portion between the first and second portions of the first electrode and electrically connected to the second terminal through the second conductive member.

2. The semiconductor device according to claim 1 , further comprising:

a die pad on which the IC chip is mounted;

a first lead electrically connected to the first terminal;

a second lead electrically connected to the second terminal; and

a sealing resin covering the IC chip and the first silicon capacitor.

3. The semiconductor device according to claim 1 , wherein

the IC chip includes a first circuit electrically connected to the first terminal and the second terminal, and

the first silicon capacitor is positioned directly above the first circuit.

4. The semiconductor device according to claim 1 , further comprising:

a second silicon capacitor on the first surface and having a third electrode and a fourth electrode on a third surface that faces the first surface;

a fourth terminal on the first surface of the IC chip;

a fifth terminal on the first surface of the IC chip, wherein

the third electrode is electrically connected to the fourth terminal through a fourth conductive member, and

the fourth electrode is electrically connected to the fifth terminal through a fifth conductive member.

5. The semiconductor device according to claim 2 , further comprising:

an inductor electrically connected to the first terminal and the first lead and covered by the sealing resin.

6. The semiconductor device according to claim 4 , wherein

the IC chip further includes a second circuit electrically connected to the fourth terminal and the fifth terminal, and

the second silicon capacitor is positioned directly above the second circuit.

7. The semiconductor device according to claim 4 , wherein

the first and third electrodes are either a positive electrode or a negative electrode,

the second fourth electrodes are the other one of a positive electrode or a negative electrode opposite of the first and third electrodes, and

a direction from the first electrode toward the second electrode is opposite to a direction from the third electrode toward the fourth electrode.

8. A semiconductor device, comprising:

a die pad;

an integrated circuit (IC) chip on the die pad and having a first terminal and a second terminal;

a first silicon capacitor including a first electrode and a second electrode, the first electrode being electrically connected to the first terminal through a first wiring member, and the second electrode being electrically connected to the second terminal through a second wiring member;

a first lead electrically connected to the first terminal;

a second lead electrically connected to the second terminal; and

a sealing resin covering the IC chip and the first silicon capacitor, wherein

the first silicon capacitor is between the IC chip and the die pad, and

a planar area of the first silicon capacitor is greater than a planar area of the IC chip when viewed in a plan view.

9. The semiconductor device according to claim 8 , wherein the first silicon capacitor is on the die pad.

10. The semiconductor device according to claim 8 , wherein the IC chip is above the first silicon capacitor.

11. A semiconductor device, comprising:

a die pad;

an integrated circuit (IC) chip on the die pad and having a first terminal and a second terminal;

a first silicon capacitor including a first electrode and a second electrode, the first electrode being electrically connected to the first terminal through a first wiring member, and the second electrode being electrically connected to the second terminal through a second wiring member;

a first lead electrically connected to the first terminal;

a second lead electrically connected to the second terminal;

a sealing resin covering the IC chip and the first silicon capacitor; and

a second silicon capacitor on the first silicon capacitor and including a third electrode and a fourth electrode, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2021
From: HOSOKAWA, ATSUSHI; SHINTOKU, YASUHISA; NOINE, YASUKAZU; KATAYAMA, YOSHIHARU
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 056531/0805 →
Priority Claims (1)
JP 2020-153215 · Sep 11, 2020 · national
Continuity (1)
Related Publication 20220084995A1 · Mar 17, 2022