Display substrate, manufacturing method thereof, display panel and display device

1. A display substrate, comprising:

a base substrate comprising a first area and a second area;

a low temperature poly-silicon transistor arranged in the first area; and

an oxide transistor arranged in the second area;

wherein the first area and the second area are not overlapped with each other;

the low temperature poly-silicon transistor comprises a poly-silicon active layer;

the oxide transistor comprises a first gate electrode;

the first gate electrode is arranged in a same layer as the poly-silicon active layer; and

a material of the first gate electrode is heavily-doped poly-silicon;

wherein the low temperature poly-silicon transistor further comprises: a second gate electrode, a first source electrode, and a first drain electrode;

wherein the second gate electrode, the first source electrode, and the first drain electrode are sequentially disposed on a side, facing away from the base substrate, of a layer where the poly-silicon active layer is located;

the first source electrode and the first drain electrode are electrically connected with the poly-silicon active layer; and

the oxide transistor further comprises: an oxide active layer, arranged between a layer where the second gate electrode is located and a layer where the first source electrode and the first drain electrode are located;

a third gate electrode, arranged between the oxide active layer and the layer where the first source electrode and the first drain electrode are located; and

a second source electrode and a second drain electrode, which are arranged in a same layer as the layer where the first source electrode and the first drain electrode are located;

wherein the second source electrode and the second drain electrode are electrically connected with the oxide active layer.

2. The display substrate of claim 1 , further comprising:

a first gate insulating layer, arranged between the layer where the first gate electrode is located and a layer where the oxide active layer is located;

a second gate insulating layer, arranged between the layer where the oxide active layer is located and a layer where the third gate electrode is located; and

an interlayer insulating layer, arranged between the layer where the oxide active layer is located and a layer where the second source electrode and the second drain electrode are located;

wherein the first source electrode and the first drain electrode are electrically connected with the poly-silicon active layer through a first via hole penetrating through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer;

the second source electrode and the second drain electrode are electrically connected with the oxide active layer through a second via hole penetrating through the second gate insulating layer and the interlayer insulating layer; and

the first via hole and the second via hole are formed in a same process.

3. The display substrate of claim 1 , wherein the base substrate further comprises:

a third area;

wherein the third area is not overlapped with either the first area or the second area;

the third area is provided with a capacitor;

the capacitor comprises:

a first electrode, arranged in a same layer as the layer where the second gate electrode is located; and

a second electrode, arranged in a same layer as a layer where the third gate electrode is located.

4. The display substrate of claim 1 , further comprising:

a planarization layer,

a plurality of anodes, and

a pixel defining layer,

wherein the planarization layer, the plurality of anodes, and the pixel defining layer are arranged in sequence on a side, facing away from the base substrate, of the layer where the first source electrode and the first drain electrode are located;

the pixel defining layer is provided with a plurality of pixel openings, and each of the plurality of pixel openings is correspondingly internally provided with a respective one of the plurality of anodes; and

each of the plurality of anodes is correspondingly electrically connected with the first drain electrode through a third via hole penetrating through the planarization layer.

5. The display substrate of claim 1 , wherein the oxide transistor is a switch transistor, and the low temperature poly-silicon transistor is a drive transistor.

6. A display panel, comprising the display substrate of claim 1 .

7. The display panel of claim 6 , further comprising:

a first gate insulating layer, arranged between the layer where the first gate electrode is located and a layer where the oxide active layer is located;

a second gate insulating layer, arranged between the layer where the oxide active layer is located and a layer where the third gate electrode is located; and

an interlayer insulating layer, arranged between the layer where the oxide active layer is located and a layer where the second source electrode and the second drain electrode are located;

wherein the first source electrode and the first drain electrode are electrically connected with the poly-silicon active layer through a first via hole penetrating through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer;

the second source electrode and the second drain electrode are electrically connected with the oxide active layer through a second via hole penetrating through the second gate insulating layer and the interlayer insulating layer; and

the first via hole and the second via hole are formed in a same process.

8. The display panel of claim 6 , wherein the base substrate further comprises:

a third area;

wherein the third area is not overlapped with either the first area or the second area; and

the third area is provided with a capacitor;

the capacitor comprises:

a first electrode, arranged in a same layer as the layer where the second gate electrode is located; and

a second electrode, arranged in a same layer as a layer where the third gate electrode is located.

9. The display panel of claim 6 , further comprising:

a planarization layer,

a plurality of anodes, and

a pixel defining layer;

wherein the planarization layer, the plurality of anodes, and the pixel defining layer are arranged in sequence on a side, facing away from the base substrate, of the layer where the first source electrode and the first drain electrode are located;

the pixel defining layer is provided with a plurality of pixel openings, and each of the plurality of pixel openings is correspondingly internally provided with a respective one of the plurality of anodes; and

each of the plurality of anodes is correspondingly electrically connected with first drain electrode through a third via hole penetrating through the planarization layer.

10. The display panel of claim 6 , wherein the oxide transistor is a switch transistor, and the low temperature poly-silicon transistor is a drive transistor.

11. A display device, comprising the display panel of claim 6 .

12. The display device of claim 11 , further comprising:

a first gate insulating layer, arranged between the layer where the first gate electrode is located and a layer where the oxide active layer is located;

a second gate insulating layer, arranged between the layer where the oxide active layer is located and a layer where the third gate electrode is located; and

an interlayer insulating layer, arranged between the layer where the oxide active layer is located and a layer where the second source electrode and the second drain electrode are located;

wherein the first source electrode and the first drain electrode are electrically connected with the poly-silicon active layer through a first via hole penetrating through the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer;

the second source electrode and the second drain electrode are electrically connected with the oxide active layer through a second via hole penetrating through the second gate insulating layer and the interlayer insulating layer; and

the first via hole and the second via hole are formed in a same process.

13. The display device of claim 11 , wherein the base substrate further comprises:

a third area;

wherein the third area is not overlapped with either the first area or the second area; and

the third area is provided with a capacitor;

the capacitor comprises:

a first electrode, arranged in a same layer as the layer where the second gate electrode is located; and

a second electrode, arranged in a same layer as a layer where the third gate electrode is located.