IP Library › Granted Patent US 11,709,727
Granted Patent B2
US 11,709,727 · App. 17/216,901 · Granted Jul 25, 2023

Managing error-handling flows in memory devices

Inventors: Kishore Kumar Muchherla (Fremont, CA); Shane Nowell (Boise, ID); Mustafa N. Kaynak (San Diego, CA); Sampath K. Ratnam (Boise, ID); Peter Feeley (Boise, ID); Sivagnanam Parthasarathy (Carlsbad, CA); Devin M. Batutis (San Jose, CA); Xiangang Luo (Fremont, CA)
Assignee: Micron Technology, Inc.
G06F11/0793G06F11/0727G06F11/0751
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Quick Facts
Patent No.
US 11,709,727
App. No.
17/216,901
Granted
Jul 25, 2023
Kind
B2
Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an ordered set of error-handling operations to be performed to the data, determining a most recently performed error-handling operation associated with the voltage offset bin; adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

Claims (44)

1. A system comprising:

a memory device; and

a processing device, operatively coupled to the memory device, to perform operations comprising:

detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin;

determining an ordered set of error-handling operations to be performed to the data;

determining a most recently performed error-handling operation associated with the voltage offset bin, wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin;

adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and

performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

2. The system of claim 1 , wherein the ordered set of error-handling operations is based on the voltage offset bin associated with the block.

3. The system of claim 1 , wherein the processing device is to perform further operations comprising:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

4. The system of claim 1 , wherein the processing device is to perform further operations comprising:

maintaining, in a metadata table, an indication of a location of the predetermined position in the error-handling flow.

5. The system of claim 1 , wherein the processing device is to perform further operations comprising:

in response to an error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the error-handling operation.

6. The system of claim 1 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

7. The system of claim 1 , wherein the order is specified in a metadata table.

8. A method, comprising:

detecting a read error with respect to data residing in a block of a memory device;

determining, based on a voltage offset bin associated with the block, an ordered set of error-handling operations to be performed to the data;

determining a most recently performed error-handling operation, wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error; and

performing the error-handling most recently performed operation as a first error-handing operation of the error-handling flow.

9. The method of claim 8 , further comprising:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

10. The method of claim 8 , further comprising:

in response to an error-handling operation of the set of error-handling operations recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the error-handling operation.

11. The method of claim 8 , further comprising:

maintaining, in a metadata table, an indication that the most recently performed error-handling operation is to be performed first in a subsequent error-handling flow.

12. The method of claim 8 , wherein an order of the ordered set of error-handling operations is specified in a metadata table.

13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, performs operations comprising:

detecting a read error with respect to data residing in a block of a memory device, wherein the block is associated with a voltage offset bin;

determining an ordered set of error-handling operations to be performed to the data,

determining a most recently performed error-handling operation associated with the voltage offset bin, wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin;

adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and

performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.

14. The non-transitory computer-readable storage medium of claim 13 , wherein the ordered set of error-handling operations is based on the voltage offset bin associated with the block.

15. The non-transitory computer-readable storage medium of claim 13 , wherein the processing device to perform further operations comprising:

maintaining, in a metadata table, a record indicating an error-handling operation that successfully recovered data.

16. The non-transitory computer-readable storage medium of claim 14 , wherein the processing device to perform further operations comprising:

maintaining, in a metadata table, an indication of a location of the predetermined position in the error-handling flow.

17. The non-transitory computer-readable storage medium of claim 13 , wherein the processing device is to perform further operations comprising:

in response to an error-handling operation of the set of error-handling operations in the adjusted order recovering data associated with the read error, updating a metadata table by replacing the most recently performed error-handling operation with the error-handling operation.

18. The non-transitory computer-readable storage medium of claim 13 , wherein the predetermined position is set during at least one of programming or calibration of the memory device.

19. The non-transitory computer-readable storage medium of claim 13 , wherein the order is specified in a metadata table.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2022
From: MUCHHERLA, KISHORE KUMAR; NOWELL, SHANE; KAYNAK, MUSTAFA N.; RATNAM, SAMPATH K.; FEELEY, PETER; PARTHASARATHY, SIVAGNANAM; BATUTIS, DEVIN M.; LUO, XIANGANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 058679/0740 →
Continuity (1)
Related Publication 20220318086A1 · Oct 6, 2022
Cited By (1)
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