Display panel, manufacturing method thereof and display device

1. A display panel, comprising a base substrate, drive circuits and pixel units disposed on one side of the base substrate, wherein the display panel comprises a first display region and a second display region;

wherein the first display region comprises a plurality of first pixel units, the second display region comprises a plurality of second pixel units, a pixel unit density of the first pixel units is less than a pixel unit density of the second pixel units;

wherein the first display region further comprises a plurality of first drive circuits, and the plurality of first drive circuits are electrically connected to the plurality of first pixel units;

wherein the second display region further comprises a plurality of second drive circuits, and the plurality of second drive circuits are electrically connected to the plurality of second pixel units;

wherein a first drive circuit of the plurality of first drive circuits comprises a first drive transistor and at least one first additional transistor, a second drive circuit of the plurality of second drive circuits comprises a second drive transistor and a second additional transistor, a number of first additional transistors in the first drive circuit is less than a number of second additional transistors in the second drive circuit, and an area of the orthographic projection of a channel area of the first drive transistor on the base substrate is less than an area of the orthographic projection of a channel area of the second drive transistor on the base substrate.

2. The display panel of claim 1 , wherein the first drive circuit comprises the first drive transistor and a first additional transistor, the first drive transistor and the first additional transistor comprise monocrystalline silicon transistors;

wherein the first drive transistor comprises a first input electrode, a first output electrode and a first control electrode, the first additional transistor comprises a second input electrode, a second output electrode and a second control electrode, and wherein the second output electrode is electrically connected to the first control electrode;

wherein the first drive circuit further comprises a voltage signal receiving terminal, a scanning signal receiving terminal, a data signal receiving terminal and an anode connection terminal, the voltage signal receiving terminal is electrically connected to the first input electrode, the scanning signal receiving terminal is electrically connected to the second control electrode, the data signal receiving terminal is electrically connected to the second input electrode and the anode connection terminal is electrically connected to the first output electrode;

wherein the display panel further comprises an anode, a data signal line, a scanning signal line and a voltage signal line disposed on one side of the base substrate, a data signal output terminal, a scanning signal output terminal and a voltage signal output terminal located in the first display region and disposed on one side of the base substrate; and

the voltage signal output terminal is electrically connected to the voltage signal line and the voltage signal receiving terminal separately, the scanning signal output terminal is electrically connected to the scanning signal line and the scanning signal receiving terminal separately, the data signal output terminal is electrically connected to the data signal line and the data signal receiving terminal separately, and the anode is electrically connected to the anode connection terminal.

3. The display panel of claim 2 , wherein the voltage signal output terminal, the scanning signal output terminal, and the data signal output terminal are disposed in a same layer and disposed on one side of the first drive circuit facing away from the anode; and

wherein the first drive circuit is disposed between the anode and a plane on which the voltage signal output terminal is located.

4. The display panel of claim 1 , wherein the first drive circuit comprises the first drive transistor and a first additional transistor, the first drive transistor comprises a monocrystalline silicon transistor, and the first additional transistor comprises a polycrystalline silicon transistor;

wherein the first drive transistor comprises a first input electrode, a first output electrode, a first control electrode, a voltage signal receiving terminal, a control signal receiving terminal, and an anode connection terminal, wherein the voltage signal receiving terminal is electrically connected to the first input electrode, the control signal receiving terminal is electrically connected to the first control electrode, and the anode connection terminal is electrically connected to the first output electrode;

wherein the display panel further comprises a voltage signal line, a scanning signal line, a data signal line, and an anode disposed on one side of the base substrate, and the first additional transistor, a voltage signal output terminal and a control signal output terminal located disposed on one side of the base substrate and located in the first display region;

wherein the first additional transistor comprises a second input electrode, a second output electrode, and a second control electrode; and

wherein the voltage signal output terminal is electrically connected to the voltage signal line and the voltage signal receiving terminal separately, the control signal output terminal is electrically connected to the second output electrode and the control signal receiving terminal separately, the scanning signal line is electrically connected to the second control electrode, the data signal line is electrically connected to the second input electrode, and the anode is electrically connected to the anode connection terminal.

5. The display panel of claim 4 , wherein the voltage signal output terminal and the control signal output terminal are disposed on a same layer and disposed on one side of the first drive transistor facing away from the anode; and

wherein the first drive transistor is disposed between the anode and a plane on which the voltage signal output terminal is located.

6. The display panel of claim 1 , wherein the first drive transistor and the first additional transistor comprise a monocrystalline silicon active layer, the second drive transistor and the second additional transistor comprise a polycrystalline silicon active layer; and

the monocrystalline silicon active layer and the polycrystalline silicon active layer are configured in different layers.

7. The display panel of claim 6 , wherein the monocrystalline silicon active layer is disposed on one side of the polycrystalline silicon active layer facing away from the base substrate; or

wherein the monocrystalline silicon active layer is disposed on one side of the polycrystalline silicon active layer facing towards the base substrate;

wherein the display panel further comprises a light-blocking layer, wherein the light-blocking layer is disposed between the monocrystalline silicon active layer and the base substrate, and a vertical projection of the light-blocking layer on a plane on which the base substrate is located is at least partially overlapped with a vertical projection of the monocrystalline silicon active layer on the plane on which the base substrate is located.

8. The display panel of claim 1 , wherein each of the first drive transistor and the at least one first additional transistor comprises a polycrystalline silicon transistor, each of the second drive transistor and the second additional transistor comprises the polycrystalline silicon transistor;

wherein the each of the first drive transistor and the at least one first additional transistor comprises a first polycrystalline silicon active layer, the each of the second drive transistor and the second additional transistor comprises a second polycrystalline silicon active layer, and a grain size of the first polycrystalline silicon active layer is larger than a grain size of the second polycrystalline silicon active layer; and

wherein the first polycrystalline silicon active layer and the second polycrystalline silicon active layer are disposed in a same layer.

9. The display panel of claim 8 , wherein the grain size of the first polycrystalline silicon active layer is D 1 , and the grain size of the second polycrystalline silicon active layer is D 2 , wherein 50 micron (μm)≤D 1 ≤5 millimeter (mm) and 10 nanometer (nm)≤D 2 ≤10 μm.

10. The display panel of claim 8 , wherein an electron mobility of the first polycrystalline silicon active layer is V, wherein V≥500 cm 2 /(volt·second).

11. The display panel of claim 1 , wherein the first display region further comprises a first signal line connected to the first drive circuit, and the second display region further comprises a second signal line connected to the second drive circuit, wherein a line width of the first signal line is d 1 , and a line width of the second signal line is d 2 , wherein 500 nm≤d 1 ≤2 μm and d 2 ≥2 μm.

12. The display panel of claim 1 , wherein the display panel further comprises a transition display region between the first display region and the second display region;

wherein the transition display region comprises a plurality of third pixel units and a third drive circuit, and a pixel unit density of the third pixel units is greater than the pixel unit density of the first pixel units and is less than the pixel unit density of the second pixel units; and

wherein the third drive circuit comprises a third drive transistor and at least one third additional transistor, a number of third additional transistors in the third drive circuit is greater than the number of first additional transistors in the first drive circuit and is less than the number of second additional transistors in the second drive circuit; and

wherein an area of the orthographic projection of a channel area of the third drive transistor on the base substrate is larger than the area of the orthographic projection of the channel area of the first drive transistor on the base substrate, and is smaller than the area of the orthographic projection of the channel area of the second drive transistor on the base substrate.

13. The display panel of claim 1 , wherein a width of the channel area of the first drive transistor is W 1 in a direction perpendicular to an extension direction of an active layer of the first drive transistor, a width of the channel area of the second drive transistor is W 2 in a direction perpendicular to an extension direction of an active layer of the second drive transistor; and

wherein a length of the channel area of the first drive transistor is L 1 , a length of the channel area of the second drive transistor is L 2 , wherein

1

60

<

W

⁢

1

·

L

⁢

1

W

⁢

2

·

L

⁢

2

<

1

2

.

14. A manufacturing method for a display panel, wherein the display panel comprises a first display region and a second display region;

wherein the manufacturing method comprises:

providing a base substrate, and preparing pixel units and drive circuits disposed on one side of the base substrate;

preparing first drive circuits in the first display region, and preparing second drive circuits in the second display region, one of the first drive circuits comprises a first drive transistor and at least one first additional transistor, one of the second drive circuits comprises a second drive transistor and at least one second additional transistor, a number of first additional transistors in the first drive circuit is less than a number of second additional transistors in the second drive circuit, an area of the orthographic projection of a channel area of the first drive transistor on the base substrate is smaller than an area of the orthographic projection of a channel area of the second drive transistor on the base substrate; and

preparing a plurality of first pixel units in the first display region, preparing a plurality of second pixel units in the second display region, the plurality of first pixel units are electrically connected to the first drive circuits, and the plurality of second pixel units are electrically connected to the second drive circuits, and a pixel unit density of the plurality of first pixel units is less than a pixel unit density of the plurality of second pixel units.

15. The manufacturing method of claim 14 , wherein one of the first drive circuits comprises the first drive transistor and one first additional transistor, the first drive transistor and the first additional transistor comprise monocrystalline silicon transistors;

wherein the preparing the first drive circuits in the first display region comprises:

preparing a plurality of the first drive circuits on a monocrystalline silicon wafer and obtaining a first drive circuit encapsulation structure, one of the first drive circuits comprises the first drive transistor, one first additional transistor, a voltage signal receiving terminal, a scanning signal receiving terminal, a data signal receiving terminal and an anode connection terminal; the first drive transistor comprises a first input electrode, a first output electrode, and a first control electrode, and the first additional transistor comprises a second input electrode, a second output electrode, and a second control electrode; wherein the second output electrode is electrically connected to the first control electrode, the voltage signal receiving terminal is electrically connected to the first input electrode, the scanning signal receiving terminal is electrically connected to the second control electrode, the data signal receiving terminal is electrically connected to the second input electrode, and the anode connection terminal is electrically connected to the first output electrode;

preparing a voltage signal line, a scanning signal line, a data signal line, and an anode on the base substrate, and preparing a voltage signal output terminal, a scanning signal output terminal, and a data signal output terminal in an area on the base substrate corresponding to the first display region; the voltage signal output terminal is electrically connected to the voltage signal line, the scanning signal output terminal is electrically connected to the scanning signal line, and the data signal output terminal is electrically connected to the data signal line; and

transferring the first drive circuit encapsulation structure to the first display region on the base substrate, so that the voltage signal output terminal is electrically connected to the voltage signal receiving terminal, and the scanning signal output terminal is electrically connected to the scanning signal receiving terminal, the data signal output terminal is electrically connected to the data signal receiving terminal, and the anode is electrically connected to the anode connection terminal.

16. The manufacturing method of claim 14 , wherein the first drive circuits comprise the first drive transistor and a first additional transistor, wherein the first drive transistor comprises a monocrystalline silicon transistor, and the first additional transistor comprises a polycrystalline silicon transistor;

wherein the preparing the first drive circuits in the first display region comprises:

preparing a plurality of first drive transistors on a monocrystalline silicon wafer to obtain a first sub-drive circuit encapsulation structure, wherein the first drive transistor comprises a first input electrode, a first output electrode, a first control electrode, a voltage signal receiving terminal, a control signal receiving terminal and an anode connection terminal, wherein the voltage signal receiving terminal is electrically connected to the first input electrode, the control signal receiving terminal is electrically connected to the first control electrode, and the anode connection terminal is electrically connected to the first output electrode;

preparing a voltage signal line, a scanning signal line, a data signal line, and an anode on the base substrate, and preparing a first additional transistor, a voltage signal output terminal and a control signal output terminal in an area on the base substrate corresponding to the first display region, wherein the first additional transistor comprises a second input electrode, a second output electrode and a second control electrode, wherein the voltage signal output terminal is electrically connected to the voltage signal line, the control signal output terminal is electrically connected to the second output electrode, the scanning signal line is electrically connected to the second control electrode, and the data signal line is electrically connected to the second input electrode;

transferring the first sub-drive circuit encapsulation structure to the first display region on the base substrate, so that the voltage signal output terminal is electrically connected to the voltage signal receiving terminal, and the control signal output terminal is electrically connected to the control signal receiving terminal, and the anode is electrically connected to the anode connection terminal.

17. The manufacturing method of claim 14 , wherein the first drive transistor and the first additional transistor comprise monocrystalline silicon transistors;

wherein the preparing the first drive circuits in the first display region comprises:

preparing a monocrystalline silicon active layer in the first display region; and

preparing a first input electrode, a first output electrode, and a first control electrode of the first drive transistor, a second input electrode, a second output electrode and a second control electrode of the first additional transistor on the monocrystalline silicon active layer.

18. The manufacturing method of claim 17 , wherein the preparing the monocrystalline silicon active layer in the first display region comprises:

providing a monocrystalline silicon wafer;

performing hydrogen ion implantation on a first wafer surface of the monocrystalline silicon wafer;

attaching the monocrystalline silicon wafer to the base substrate in a manner in which the first wafer surface faces towards the base substrate;

heating a second wafer surface of the monocrystalline silicon wafer and a surface of the base substrate facing away from the monocrystalline silicon wafer, obtaining a monocrystalline silicon active layer on the base substrate, wherein the second wafer surface is opposite to the first wafer surface; and

removing the monocrystalline silicon wafer excluding the monocrystalline silicon active layer on the base substrate and obtaining the monocrystalline silicon active layer disposed on the base substrate.

19. The manufacturing method of claim 14 , wherein each of the first drive transistor and the first additional transistor comprises a polycrystalline silicon transistor, each of the second drive transistor and the second additional transistor comprises the polycrystalline silicon transistor; and

wherein the preparing the first drive circuits in the first display region and preparing the second drive circuits in the second display region comprises:

preparing a polycrystalline silicon layer disposed on one side of the base substrate;

performing excimer laser annealing on the polycrystalline silicon layer in the first display region, obtaining a first polycrystalline silicon active layer in the first display region and a second polycrystalline silicon active layer in the second display region, wherein a grain size of the first polycrystalline silicon active layer is larger than a grain size of the second polycrystalline silicon active layer.

20. A display device, comprising a display panel, wherein the display panel comprises: a base substrate, drive circuits and pixel units disposed on one side of the base substrate, wherein the display panel comprises a first display region and a second display region;

wherein the first display region comprises a plurality of first pixel units, the second display region comprises a plurality of second pixel units, a pixel unit density of the first pixel units is less than a pixel unit density of the second pixel units;

wherein the first display region further comprises a plurality of first drive circuits, and the plurality of first drive circuits are electrically connected to the plurality of first pixel units;

wherein the second display region further comprises a plurality of second drive circuits, and the plurality of second drive circuits are electrically connected to the plurality of second pixel units;

wherein one first drive circuit of the plurality of first drive circuits comprises a first drive transistor and at least one first additional transistor, one second drive circuit of the plurality of second drive circuits comprises a second drive transistor and a second additional transistor, a number of first additional transistors in the first drive circuit is less than a number of second additional transistors in the second drive circuit, and an area of the orthographic projection of a channel area of the first drive transistor on the base substrate is less than an area of the orthographic projection of a channel area of the second drive transistor on the base substrate; and

wherein the display device further comprises a sensor, and wherein the first display region is reused as a sensor reserved area.