Three dimensional (3D) double gate semiconductor
Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.
1. An apparatus comprising a double gate metal oxide semiconductor (MOS) transistor, wherein the double gate MOS transistor comprises:
a first back gate;
a second back gate;
a first dielectric layer disposed on the first back gate and on the second back gate;
an MX2 material layer disposed on the first dielectric layer;
a second dielectric layer disposed on the MX2 material layer;
a work function metal (WFM) disposed on the second dielectric layer;
a front gate disposed on the WFM, wherein the front gate fills a space between the first back gate and the second back gate;
an upper dielectric layer, wherein at least a portion of the double gate MOS transistor is in the upper dielectric layer;
a shallow trench isolation layer located below the upper dielectric layer; and
a silicon substrate located below the shallow trench isolation layer,
wherein the first back gate comprises a first fin that comprises N+ doped Silicon, wherein the first back gate is coupled to a P-well disposed in the silicon substrate, wherein the second back gate comprises a second fin that comprises N+ doped Silicon, and wherein the second back gate is coupled to the P-well disposed in the silicon substrate.
2. The apparatus of claim 1 , wherein the first back gate, the second back gate, and the front gate each comprises Tungsten (W), Titanium (Ti), Titanium Nitride (TiN), Tantalum (Ta), Tantalum Nitride (TaN), or polysilicon.
3. The apparatus of claim 1 , wherein the first dielectric layer and the second dielectric layer comprise Hafnium Oxide (HfOx).
4. The apparatus of claim 1 , wherein the MX2 material layer disposed over the first back gate is separated from the MX2 material layer disposed over the second back gate, and the second dielectric layer disposed over the first back gate is separated from the second dielectric layer disposed over the second back gate.
5. The apparatus of claim 1 , wherein the MX2 material layer comprises a layer of transition metal atoms between two layers of chalcogen atoms.
6. The apparatus of claim 5 , wherein the layer of transition metal atoms comprises at least one of: Molybdenum (Mo), Tungsten (W), Tin (Sn), Hafnium (Hf), Zirconium (Zr), Platinum (Pt), or any combination thereof.
7. The apparatus of claim 5 , wherein the layers of chalcogen atoms comprise at least one of: Sulphur (S), Selenium (Se), Tellurium (Te), or any combination thereof.
8. The apparatus of claim 1 , wherein the WFM is an N-type WFM.
9. The apparatus of claim 1 , wherein the double gate MOS transistor is an N-type MOS (N-MOS) transistor or a P type MOS (P MOS) transistor.
10. The apparatus of claim 1 , further comprising:
an optical waveguide located in the silicon substrate.
11. The apparatus of claim 1 , further comprising a second double gate MOS transistor, wherein the second double gate MOS transistor comprises:
a first back gate;
a second back gate;
a first dielectric layer disposed on the first back gate and on the second back gate;
an MX2 material layer disposed on the first dielectric layer;
a second dielectric layer disposed on the MX2 material layer;
a work function metal (WFM) disposed on the second dielectric layer; and
a front gate disposed on the WFM, wherein the front gate fills a space between the first back gate and the second back gate.
12. The apparatus of claim 11 , wherein the second double gate MOS transistor is a P-type MOS transistor.
13. An apparatus comprising a double gate metal oxide semiconductor (MOS) transistor, wherein the double gate MOS transistor comprises:
a first back gate;
a second back gate;
a first dielectric layer disposed on the first back gate and on the second back gate;
an MX2 material layer disposed on the first dielectric layer;
a second dielectric layer disposed on the MX2 material layer;
a work function metal (WFM) disposed on the second dielectric layer;
a front gate disposed on the WFM, wherein the front gate fills a space between the first back gate and the second back gate;
an upper dielectric layer, wherein at least a portion of the double gate MOS transistor is in the upper dielectric layer;
a shallow trench isolation layer located below the upper dielectric layer; and
a silicon substrate located below the shallow trench isolation layer,
wherein the first back gate comprises a first fin that comprises P+ doped Silicon, wherein the first back gate is coupled to an N-well disposed in the silicon substrate, wherein the second back gate comprises a second fin that comprises P+ doped Silicon, and wherein the second back gate is coupled to the N-well disposed in the silicon substrate.
14. A method for fabricating a double gate metal oxide semiconductor (MOS) transistor, comprising:
forming a first back gate;
forming a second back gate;
depositing a first dielectric layer on the first back gate and on the second back gate;
depositing an MX2 material layer on the first dielectric layer;
depositing a second dielectric layer on the MX2 material layer;
depositing a work function metal (WFM) on the second dielectric layer;
forming a front gate on the WFM, wherein the front gate fills a space between the first back gate and the second back gate;
depositing an upper dielectric layer, wherein at least a portion of the double gate MOS transistor is in the upper dielectric layer; and
forming a shallow trench isolation layer located below the upper dielectric layer,
wherein a silicon substrate locates below the shallow trench isolation layer, wherein the first back gate comprises a first fin that comprises N+ doped Silicon, wherein the first back gate is coupled to a P-well disposed in the silicon substrate, wherein the second back gate comprises a second fin that comprises N+ doped Silicon, and wherein the second back gate is coupled to the P-well disposed in the silicon substrate.
15. The method of claim 14 , wherein the MX2 material layer disposed over the first back gate is separated from the MX2 material layer disposed over the second back gate, and the second dielectric layer disposed over the first back gate is separated from the second dielectric layer disposed over the second back gate.
16. The method of claim 14 , wherein the MX2 material layer comprises a layer of transition metal atoms between two layers of chalcogen atoms.
17. The method of claim 16 , wherein the layer of transition metal atoms comprises at least one of: Molybdenum (Mo), Tungsten (W), Tin (Sn), Hafnium (Hf), Zirconium (Zr), Platinum (Pt), or any combination thereof.
18. The method of claim 16 , wherein the layers of chalcogen atoms comprise at least one of: Sulphur (S), Selenium (Se), Tellurium (Te), or any combination thereof.
19. The method of claim 14 , wherein the double gate MOS transistor is an N-type MOS transistor.
20. A method for fabricating a double gate metal oxide semiconductor (MOS) transistor, comprising:
forming a first back gate;
forming a second back gate;
depositing a first dielectric layer on the first back gate and on the second back gate;
depositing an MX2 material layer on the first dielectric layer;
depositing a second dielectric layer on the MX2 material layer;
depositing a work function metal (WFM) on the second dielectric layer;
forming a front gate on the WFM, wherein the front gate fills a space between the first back gate and the second back gate;
depositing an upper dielectric layer, wherein at least a portion of the double gate MOS transistor is in the upper dielectric layer; and
forming a shallow trench isolation layer located below the upper dielectric layer,
wherein a silicon substrate locates below the shallow trench isolation layer, wherein the first back gate comprises a first fin that comprises P+ doped Silicon, wherein the first back gate is coupled to an N-well disposed in the silicon substrate, wherein the second back gate comprises a second fin that comprises P+ doped Silicon, and wherein the second back gate is coupled to the N-well disposed in the silicon substrate.