Low frequency power supply spur reduction in clock signals
Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.
1. A circuit for clock distribution, the circuit comprising:
a plurality of logic inverters coupled in series and configured to drive a clock signal;
a current-starved inverter coupled in parallel with a logic inverter in the plurality of logic inverters; and
a biasing circuit having a first bias node and a second bias node coupled to the current-starving inverter and configured to control a current through the current-starved inverter, wherein the biasing circuit comprises:
a reference current source;
a first current mirror coupled to the reference current source;
a second current mirror coupled to the first current mirror;
a third current mirror coupled to the second current mirror;
a fourth current mirror coupled to the third current mirror and comprising the second bias node and a first current-setting transistor in the current-starved inverter; and
a fifth current mirror coupled to the fourth current mirror and comprising the first bias node and a second current-setting transistor in the current-starved inverter.
2. The circuit of claim 1 , wherein the logic inverter has a power input coupled to a power supply rail configured to have a power supply voltage and wherein the current-starved inverter is configured to:
decrease an inverter current and increase a delay in the clock signal when the power supply voltage increases; and
increase the inverter current and decrease the delay in the clock signal when the power supply voltage decreases.
3. The circuit of claim 1 , wherein the current-starved inverter comprises:
a first transistor having a gate coupled to an input of the logic inverter and having a source coupled to a power supply rail;
a second transistor having a gate coupled to the first bias node, having a source coupled to a drain of the first transistor, and having a drain coupled to an output of the logic inverter;
a third transistor having a gate coupled to the second bias node and having a drain coupled to the output of the logic inverter; and
a fourth transistor having a gate coupled to the input of the logic inverter, having a drain coupled to a source of the third transistor, and having a source coupled to a reference potential node.
4. The circuit of claim 1 , wherein the current-starved inverter comprises:
a first transistor having a gate coupled to the first bias node and having a source coupled to a power supply rail;
a second transistor having a gate coupled to an input of the logic inverter, having a source coupled to a drain of the first transistor, and having a drain coupled to an output of the logic inverter;
a third transistor having a gate coupled to the input of the logic inverter and having a drain coupled to the output of the logic inverter; and
a fourth transistor having a gate coupled to the second bias node, having a drain coupled to a source of the third transistor, and having a source coupled to a reference potential node.
5. The circuit of claim 1 , wherein the second current mirror comprises a low-pass filter coupled between branches of the second current mirror.
6. The circuit of claim 1 , wherein:
the first current mirror is configured to set a bias voltage on a node between branches of the first current mirror;
the first current mirror comprises a current sink coupled to the second current mirror and to the third current mirror; and
the current sink is configured to be controlled by the bias voltage.
7. The circuit of claim 1 , wherein:
the second current mirror is configured to set a bias voltage on a node between branches of the second current mirror;
the second current mirror comprises a current source coupled to the third current mirror and to the fourth current mirror; and
the current source is configured to be controlled by the bias voltage.
8. The circuit of claim 1 , wherein the fifth current mirror further comprises:
a first transistor having a gate and a drain coupled to an output branch of the fourth current mirror and to the first bias node of the biasing circuit; and
a second transistor having a gate coupled to a reference potential node, wherein the first transistor or the second transistor has a source coupled to a power supply rail, the power supply rail being coupled to a power input of the logic inverter and a power input of the current-starved inverter.
9. The circuit of claim 8 , wherein:
the output branch of the fourth current mirror comprises a third transistor having a gate coupled to the power supply rail and a fourth transistor having a gate coupled to the second bias node; and
an input branch of the fourth current mirror comprises a fifth transistor having a gate coupled to the power supply rail and a sixth transistor having a gate coupled to a drain of the sixth transistor and to the second bias node.
10. A circuit for clock distribution, the circuit comprising:
a plurality of logic inverters coupled in series and configured to drive a clock signal; and
a current-starved inverter coupled in parallel with a logic inverter in the plurality of logic inverters; and
a biasing circuit having a first bias node and a second bias node coupled to the current-starving inverter and configured to control a current through the current-starved inverter, wherein the biasing circuit comprises:
a first current mirror;
a second current mirror coupled to the first current mirror;
a third current mirror coupled to the second current mirror and comprising the second bias node and a first current-setting transistor in the current-starved inverter; and
a fourth current mirror coupled to the third current mirror and comprising the first bias node and a second current-setting transistor in the current-starved inverter.
11. The circuit of claim 10 , wherein:
a power supply rail is coupled to a power input of the logic inverter and to a power input of the current-starved inverter;
the first current mirror comprises a current sink coupled to the second current mirror and to the third current mirror;
the first current mirror further comprises a high-pass filter having an input coupled to the power supply rail and having an output coupled to a control input of the current sink;
the high-pass filter is referenced to a node between first and second branches of the first current mirror; and
the current sink is disposed in a third branch of the first current mirror and is configured to be controlled by a high-pass-filtered version of a power supply voltage on the power supply rail.
12. The circuit of claim 10 , wherein the fourth current mirror further comprises:
a first transistor having a gate and a drain coupled to an output branch of the third current mirror and to the first bias node of the biasing circuit; and
a second transistor having a gate coupled to a reference potential node, wherein the first transistor or the second transistor has a source coupled to a power supply rail, the power supply rail being coupled to a power input of the logic inverter and to a power input of the current-starved inverter.
13. The circuit of claim 12 , wherein:
the output branch of the third current mirror comprises a third transistor having a gate coupled to the power supply rail and a fourth transistor having a gate coupled to the second bias node; and
an input branch of the third current mirror comprises a fifth transistor having a gate coupled to the power supply rail and a sixth transistor having a gate coupled to a drain of the sixth transistor and to the second bias node.
14. The circuit of claim 1 , further comprising another current-starved inverter coupled in parallel or in series with another logic inverter in the plurality of logic inverters.
15. A method of clock distribution, comprising:
driving a clock signal with a plurality of logic inverters coupled in series and receiving power from a power supply voltage; and
adjusting for changes in the power supply voltage using a current-starved inverter coupled in parallel with a logic inverter in the plurality of logic inverters; wherein the adjusting comprises:
generating a reference current;
generating a mirrored current based on the reference current using at least one current mirror;
sensing current changes relative to the mirrored current due to the changes in the power supply voltage;
amplifying the sensed current changes; and
controlling an inverter current of the current-starved inverter based on the amplified current changes.
16. The method of claim 15 , wherein the adjusting comprises lowering an inverter current of the current-starved inverter when the power supply voltage increases and raising the inverter current of the current-starved inverter when the power supply voltage decreases.
17. The method of claim 15 , wherein the adjusting further comprises using another current-starved inverter coupled in parallel or in series with another logic inverter in the plurality of logic inverters.