Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
1. A transmitter for a broadcast signal, comprising:
an LDPC encoder configured to generate an LDPC codeword having a length of 16200 and a code rate of 3/15 by performing accumulation with respect to memory initialized to 0, using a sequence corresponding to a parity check matrix (PCM); and
a modulator configured to generate a modulated signal corresponding to the LDPC codeword,
wherein the sequence is represented by the following Sequence Table:
Sequence Table
1st row: 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988
2nd row: 80 255 667 1511 3549 5239 5422 5497 7157 7854 11267
3rd row: 257 406 792 2916 3072 3214 3638 4090 8175 8892 9003
4th row: 80 150 346 1883 6838 7818 9482 10366 10514 11468 12341
5th row: 32 100 978 3493 6751 7787 8496 10170 10318 10451 12561
6th row: 504 803 856 2048 6775 7631 8110 8221 8371 9443 10990
7th row: 152 283 696 1164 4514 4649 7260 7370 11925 11986 12092
8th row: 127 1034 1044 1842 3184 3397 5931 7577 11898 12339 12689
9th row: 107 513 979 3934 4374 4658 7286 7809 8830 10804 10893
10th row: 2045 2499 7197 8887 9420 9922 10132 10540 10816 11876
11st row: 2932 6241 7136 7835 8541 9403 9817 11679 12377 12810
12nd row: 2211 2288 3937 4310 5952 6597 9692 10445 11064 11272.
2. The transmitter of claim 1 , wherein the LDPC codeword includes a systematic part corresponding to information bits, a first parity part and a second parity part,
wherein the accumulation is performed at parity bit addresses that are updated based on results of comparing each of previous parity bit addresses specified in respective rows of the sequence with the size of the first parity part, and
wherein the parity bit addresses are updated in accordance with the following equation:
( x+m×Q 1 )mod M 1 if x<M 1
M 1 +{( x−M 1 +m×Q 2 )mod M 2 } if x≥M 1
where x denotes the previous parity bit addresses, m is an information bit index, L is a circulant permutation matrix (CPM) size of the PCM, Q 1 is M 1 /L, M 1 is the size of the first parity part, Q 2 is M 2 /L, and M 2 is the size of the second parity part.