Schemes for SSB to paging coreset mapping in NR
The present invention relates to a user device, a base station, and data transmission and reception methods to be performed by a user device and a base station in a communications system. The user device comprises circuitry which, in operation, calculates the starting location of a paging region comprising resources in which user devices are paged, the paging region including paging information for paging said user device; and determines an offset with respect to the starting location of the paging region, the offset indicating the location of the paging information for paging said user device relative to the starting location of the paging region.
1. An integrated circuit for controlling a user equipment (UE) for transmitting and/or receiving data to/from a base station in a communication system, the integrate circuit comprising:
control circuitry which, in operation, calculates a starting location of a paging region, the paging region comprising resources in which user equipments (UEs) are paged and including paging information for paging the UE; and
receiving circuitry which, in operation, receives, from the base station, an indication of an offset with respect to the starting location of the paging region;
wherein the control circuitry, in operation, determines, based on the indication, the offset with respect to the starting location of the paging region to obtain a location of the paging information for paging the UE, the offset indicating the location of the paging information for paging the UE relative to the starting location of the paging region, and the offset indicating a frequency position in a paging location indication indicative of locations of the paging information within the paging region, and
determines an ordinal value of a location of a synchronization signal block (SSB) in a synchronization bitmap.
2. The integrated circuit according to claim 1 , wherein the calculated starting location indicates a symbol and the indication of the offset is a value indicating the absolute symbol offset with respect to the starting location.
3. The integrated circuit according to claim 1 , wherein the calculated starting location indicates a slot and the indication of the offset is a symbol index within the slot of the starting location.
4. The integrated circuit according to claim 1 , wherein the calculated starting location indicates a symbol and the indication of the offset is a combination of a slot offset with respect to the symbol of the starting location and a symbol index within the slot indicated by the slot offset.
5. The integrated circuit according to claim 1 , wherein the indication of the offset is included in remaining minimum system information (RMSI) or other system information (OSI) received from the base station.
6. The integrated circuit according to claim 1 , wherein the control circuitry, in operation, calculates the starting location of the paging region and determines the offset indicating the location of the paging information by performing respective paging occasion (PO) calculations.
7. The integrated circuit according to claim 1 , wherein the paging region is a common paging region common for each of a plurality of synchronization signal blocks.
8. The integrated circuit according to claim 1 , wherein a respective paging region from a plurality of paging regions comprising the paging region including the paging information for paging the UE is associated with a respective synchronization signal block.
9. The integrated circuit according to claim 1 , wherein the starting location of the paging region and the location of the paging information for paging the UE are locations of resources in a time domain.
10. The integrated circuit according to claim 1 , wherein the starting location of the paging region indicates a symbol or a slot.
11. The integrated circuit according to claim 1 , wherein the offset indicating the location of the paging information for paging the UE indicates a symbol and/or a slot.