Determining sums using logic circuits

1. A logic circuit implemented in hardware, the logic circuit comprising:

inputs for receiving multiple n-bit numbers, n being greater than one; and

a plurality of adders, each of the plurality of adders being capable of receiving a plurality of n-bit numbers and forming an output representing the sum of those numbers, each of the plurality of adders having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the plurality of n-bit numbers received by that adder to an operation in a respective one of the single-bit stages;

the logic circuit being configured to add the multiple n-bit numbers by:

using a splitter, splitting a first one of the multiple n-bit numbers to generate a set of non-consecutive bits of the first one of the multiple n-bit numbers;

in a first adder of the plurality of adders, adding another of the multiple n-bit numbers to a value corresponding to the set of non-consecutive bits of the first one of the multiple n-bit numbers to form a first intermediate value;

using one or more adders of the plurality of adders other than the first adder, adding the first intermediate value to a value corresponding to the bits of the said first one of the multiple n-bit numbers other than those in the said set to form a sum; and

outputting the sum.

2. A logic circuit as claimed in claim 1 , wherein n is greater than four.

3. A logic circuit as claimed in claim 1 , wherein the set of non-consecutive bits of the first one of the multiple n-bit numbers is generated by splitting, using the splitter, the first one of the multiple n-bit numbers into a first binary string comprising the bit values from the even bit positions of that n-bit number and a second binary string comprising the bit values from the odd bit positions of that n-bit number, and wherein the value corresponding to the set of non-consecutive bits is the first binary string or the second binary string.

4. A logic circuit as claimed in claim 1 , wherein the logic circuit is implemented on a FPGA, and wherein each of the plurality of single-bit stages comprises a look-up table having a 64-bit limit.

5. A logic circuit as claimed in claim 1 , wherein the logic circuit is implemented on a silicon-based integrated circuit.

6. A logic circuit as claimed in claim 1 , wherein the logic circuit is implemented on a single integrated circuit substrate.

7. A logic circuit as claimed in claim 1 , wherein the least significant bits of all the received multiple n-bit numbers are one.

8. A logic circuit as claimed in claim 1 , wherein the least significant bit of at least one of the received multiple n-bit numbers is zero.

9. A logic circuit as claimed in claim 1 , wherein each of the plurality of single-bit stages comprises a look-up table having a limit on the number of output outcomes that it can store.

10. A logic circuit as claimed in claim 1 , wherein the set of non-consecutive bits of the first one of the multiple n-bit numbers is generated by splitting, using the splitter, the first one of the multiple n-bit numbers into two or more multiple-bit binary strings, a first binary string of the two or more multiple-bit binary strings comprising the set of non-consecutive bits of the first one of the multiple n-bit numbers, and one or more other binary strings of the two or more multiple-bit binary strings comprising the bits of the said first one of the multiple n-bit numbers other than those in the said set.

11. A logic circuit as claimed in claim 10 , wherein each of the two or more multiple-bit binary strings is routed to a respective different adder of the plurality of adders.

12. A logic circuit as claimed in claim 1 , the logic circuit being configured to add, in an adder of the one or more adders of the plurality of adders other than the first adder:

the first intermediate value, or an intermediate value having a contribution from the first intermediate value; and

a value corresponding to the bits of the said first one of the multiple n-bit numbers other than those in the said set, or an intermediate value having a contribution from the bits of the said first one of the multiple n-bit numbers other than those in the said set.

13. A logic circuit, implemented in hardware, configured to determine a sum of a plurality of multiple-bit inputs, the logic circuit comprising a plurality of adders, each of the plurality of adders comprising a plurality of single-bit stages, the logic circuit being configured to:

receive the plurality of multiple-bit inputs;

split, using a splitter, a first multiple-bit input of the plurality of received multiple-bit inputs to generate a set of non-consecutive variable bit position values of the first multiple-bit input;

add, at a first adder of the plurality of adders, the set of non-consecutive variable bit position values of the first multiple-bit input of the plurality of received multiple-bit inputs to a second multiple-bit number derived from the plurality of received multiple-bit inputs so as to form an intermediate value;

add, using one or more adders of the plurality of adders other than the first adder, the intermediate value to remaining variable bit position values of the first multiple-bit input so as to form an output;

determine the sum of the plurality of multiple-bit inputs in dependence on the output; and

output the sum of the plurality of multiple-bit inputs.

14. A logic circuit as claimed in claim 13 , wherein the second multiple-bit number is selected from the plurality of multiple-bit inputs.

15. A logic circuit as claimed in claim 13 , wherein the second multiple-bit number is a set of non-consecutive bit position values of a second multiple-bit input of the plurality of received multiple-bit inputs.

16. A logic circuit as claimed in claim 13 , wherein the set of non-consecutive variable bit position values of the first multiple-bit input is generated by splitting, using the splitter, the first multiple-bit input into a first binary string comprising the bit values from the even bit positions of the first multiple-bit input and a second binary string comprising the bit values from the odd bit positions of the first multiple-bit input, and wherein the set of non-consecutive variable bit position values of the first multiple-bit input is the first binary string or the second binary string.

17. A logic circuit as claimed in claim 16 , wherein the remaining variable bit position values of the first multiple-bit input is the other of the first binary string and the second binary string.

18. A logic circuit as claimed in claim 13 , wherein the logic circuit is embodied on a FPGA, and wherein each single-bit stage comprises a look-up table having a 64-bit limit.

19. A logic circuit as claimed in claim 13 , wherein each of the plurality of single-bit stages comprises a look-up table having a limit on the number of output outcomes that it can store.

20. A logic circuit as claimed in claim 13 , wherein the set of non-consecutive variable bit position values of the first multiple-bit input is generated by splitting, using the splitter, the first multiple-bit input into two or more multiple-bit binary strings, a first binary string of the two or more multiple-bit binary strings comprising the set of non-consecutive variable bit position values of the first multiple-bit input, and one or more other binary strings of the two or more multiple-bit binary strings comprising the remaining variable bit position values of the first multiple-bit input.

21. A logic circuit as claimed in claim 20 , wherein each of the two or more multiple-bit binary strings is routed to a respective different adder of the plurality of adders.

22. A logic circuit as claimed in claim 13 , the logic circuit being configured to add, in an adder of the one or more adders of the plurality of adders other than the first adder:

the intermediate value, or a further intermediate value having a contribution from the intermediate value; and

the remaining variable bit position values of the first multiple-bit input, or an intermediate value having a contribution from the remaining variable bit position values of the first multiple-bit input.

23. A non-transitory computer readable storage medium having stored thereon hardware description code comprising configuration instructions that, when executed at a logic circuit implemented in hardware, cause the logic circuit to be configured to add multiple n-bit numbers, the logic circuit comprising:

inputs for receiving multiple n-bit numbers, n being greater than one; and

a plurality of adders, each of the plurality of adders being capable of receiving a plurality of n-bit numbers and forming an output representing the sum of those numbers, each of the plurality of adders having a plurality of single-bit stages and being configured to form the sum by subjecting successive bits of each of the plurality of n-bit numbers received by that adder to an operation in a respective one of the single-bit stages;

the logic circuit being configured to add the multiple n-bit numbers by:

using a splitter, splitting a first one of the multiple n-bit numbers so as to generate a set of non-consecutive bits of the first one of the multiple n-bit numbers;

in a first adder of the plurality of adders, adding another of the multiple n-bit numbers to a value corresponding to the set of non-consecutive bits of the first one of the multiple n-bit numbers to form a first intermediate value;

using one or more adders of the plurality of adders other than the first adder, adding the first intermediate value to a value corresponding to the bits of the said first one of the multiple n-bit numbers other than those in the said set to form a sum; and

outputting the sum.

24. A logic circuit as claimed in claim 23 , wherein each of the plurality of single-bit stages comprises a look-up table having a limit on the number of output outcomes that it can store.