Display apparatus
A display apparatus includes a substrate including a display area including a display element, a first thin film transistor disposed in the display area, the first thin film transistor including a first semiconductor layer including a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a second thin film transistor disposed in the display area, the second thin film transistor including a second semiconductor layer including an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer, a first signal line extending at a side of the first thin film transistor in a first direction, a second signal line extending at an opposite side of the first thin film transistor in the first direction, and a shielding pattern extending in the first direction, the shielding pattern at least partially overlapping the first signal line.
1. A display apparatus comprising:
a substrate comprising a display area including a display element;
a first thin film transistor disposed in the display area, the first thin film transistor comprising:
a first semiconductor layer including a silicon semiconductor; and
a first gate electrode insulated from the first semiconductor layer;
a second thin film transistor disposed in the display area, the second thin film transistor comprising:
a second semiconductor layer including an oxide semiconductor; and
a second gate electrode insulated from the second semiconductor layer;
a first signal line extending at a side of the first thin film transistor in a first direction;
a second signal line extending at an opposite side of the first thin film transistor in the first direction; and
a shielding pattern extending in the first direction, the shielding pattern at least partially overlapping the first signal line.
2. The display apparatus of claim 1 , wherein the shielding pattern and the first semiconductor layer are disposed on a same layer.
3. The display apparatus of claim 1 , wherein
the first thin film transistor comprises a driving transistor and an emission control transistor,
the second thin film transistor comprises a compensation transistor,
the first signal line is electrically connected to a gate electrode of the compensation transistor to transfer a scan signal, and
the second signal line is electrically connected to a gate electrode of the emission control transistor to transfer an emission control signal.
4. The display apparatus of claim 1 , wherein
the first thin film transistor comprises a driving transistor and a switching transistor,
a semiconductor layer in the driving transistor and a semiconductor layer in the switching transistor are integral with each other, and
the shielding pattern protrudes from a region between the semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor in the first direction in a plan view.
5. The display apparatus of claim 4 , wherein
the second thin film transistor comprises a compensation transistor, and
the shielding pattern overlaps a semiconductor layer of the compensation transistor of the second thin film transistor.
6. The display apparatus of claim 1 , wherein the shielding pattern receives a positive voltage during an emission period of the display element.
7. The display apparatus of claim 1 , wherein the shielding pattern is disposed between the substrate and the first semiconductor layer of the first thin film transistor.
8. The display apparatus of claim 7 , wherein
the first thin film transistor comprises a driving transistor and an emission control transistor,
the second thin film transistor comprises a compensation transistor, and
the first signal line includes an emission control line electrically connected to a gate electrode of the emission control transistor to transfer an emission control signal.
9. The display apparatus of claim 1 , further comprising:
a first interlayer insulating layer disposed between the first gate electrode and the second thin film transistor;
a second interlayer insulating layer overlapping the second gate electrode of the second thin film transistor;
a first power voltage line disposed on the second interlayer insulating layer, the first power voltage line extending in a second direction intersecting the first direction;
a first planarization layer overlapping the first power voltage line; and
a data line disposed on the first planarization layer, the data line extending in the second direction and at least partially overlapping the first power voltage line.
10. The display apparatus of claim 9 , further comprising:
a node connecting line disposed on the second interlayer insulating layer, the node connecting line including:
an end electrically connected to the first gate electrode of the first thin film transistor; and
an opposite end electrically connected to the second semiconductor layer of the second thin film transistor.
11. A display apparatus comprising:
a substrate comprising a display area including a display element;
a driving transistor, a switching transistor, and an emission control transistor disposed in the display area, the driving transistor, the switching transistor, and the emission control transistor each comprising a silicon semiconductor;
a compensation transistor disposed in the display area, the compensation transistor comprising an oxide semiconductor;
a first signal line extending at a side of the driving transistor in a first direction;
a second signal line extending at an opposite side of the driving transistor in the first direction; and
a shielding pattern extending in the first direction, the shielding pattern at least partially overlapping the first signal line.
12. The display apparatus of claim 11 , wherein the shielding pattern and a semiconductor layer of the driving transistor are disposed on a same layer.
13. The display apparatus of claim 11 , wherein
the first signal line is electrically connected to a gate electrode of the compensation transistor to transfer a scan signal, and
the second signal line is electrically connected to a gate electrode of the emission control transistor to transfer an emission control signal.
14. The display apparatus of claim 11 , wherein
a semiconductor layer of the driving transistor and a semiconductor layer of the switching transistor are integral with each other, and
the shielding pattern protrudes from a region between the semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor in the first direction in a plan view.
15. The display apparatus of claim 11 , wherein the shielding pattern overlaps a semiconductor layer of the compensation transistor.
16. The display apparatus of claim 11 , wherein
the compensation transistor includes an NMOS transistor,
the emission control transistor includes a PMOS transistor, and
the shielding pattern receives a positive voltage during an emission period of the display element.
17. The display apparatus of claim 11 , wherein the shielding pattern is disposed between the substrate and the semiconductor layer of the driving transistor.
18. The display apparatus of claim 17 , wherein the first signal line includes an emission control line electrically connected to a gate electrode of the emission control transistor to transfer an emission control signal.
19. The display apparatus of claim 11 , further comprising:
a first power voltage line extending in a second direction intersecting the first direction;
a first planarization layer overlapping the first power voltage line; and
a data line disposed on the first planarization layer, the data line extending in the second direction and at least partially overlapping the first power voltage line.
20. The display apparatus of claim 19 , further comprising:
a second power voltage line disposed on the first planarization layer and electrically connected to the first power voltage line.