Memory device for supporting command bus training mode and method of operating the same
There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.
1. A memory controller configured to control a command bus training (CBT) operation of a memory device, the memory controller comprising:
a clock terminal configured to transmit a clock signal;
a data clock terminal configured to transmit a data clock signal;
a first data terminal configured to transmit a first data signal;
a plurality of command/address terminals configured to transmit a command bus training (CBT) pattern during the CBT operation, the CBT pattern comprising a plurality of command/address signals; and
a plurality of second data terminals configured to transmit second data signals, the plurality of second data terminals being in one-to-one correspondence with the command/address signals during the CBT operation,
wherein the memory controller is configured to:
send a first logic level of the first data signal to the memory device in synchronization with the data clock signal and make the memory device enter a command bus training (CBT) mode;
send logic levels of the CBT pattern to the memory device in synchronization with the clock signal and receive the CBT pattern output by the memory device through the plurality of second data terminals; and
send a second logic level of the first data signal to the memory device and make the memory device exit the CBT mode.
2. The memory controller of claim 1 , wherein each signal of the CBT pattern is compared with a reference voltage to determine the logic levels of the CBT pattern in the memory device.
3. The memory controller of claim 2 , wherein a level of the reference voltage is set with a first reference voltage setting code stored in a first mode register of the memory device.
4. The memory controller of claim 3 , wherein the memory controller is further configured to transmit a second reference voltage setting code through the second data terminals and to change the level of the reference voltage in accordance with the second reference voltage setting code during the CBT mode.
5. The memory controller of claim 4 , wherein the memory controller is further configured to transmit a data mask inversion (DMI) signal, wherein the second reference voltage setting code is determined at rising edge of the DMI signal.
6. The memory controller of claim 1 , wherein the memory controller is further configured to control the memory device to perform a command/address on-die termination (CA_ODT), the CA_ODT provides each of the command/address signals with an estimated impedance matching while receiving the CBT pattern, the estimated impedance of the command/address signals being selected from termination resistance values stored in a second mode register of the memory device.
7. The memory controller of claim 6 , wherein the memory controller is further configured to control the memory device to perform a frequency set point operation right after entering the CBT mode and before receiving the CBT pattern.
8. The memory controller of claim 7 , wherein the frequency set point operation is based on operation frequency of the memory device.
9. The memory controller of claim 1 , wherein the memory controller is further configured to control the memory device to perform a data clock on-die termination (WCK_ODT), the WCK_ODT provides the data clock signal with a termination based on estimated impedance while determining a logic level of the first data signal.
10. The memory controller of claim 1 , wherein the memory controller is further configured to control the memory device to perform a data signal on-die termination (DQ_ODT), the DQ_ODT is turned off during the CBT mode, wherein the DQ_ODT provides the first and second data signals with corresponding termination during a normal write operation.
11. A memory system comprising:
a memory device configured to perform a command bus training (CBT) operation; and
a memory controller configured to transmit a command bus training (CBT) pattern to the memory device; and
wherein the memory device comprises:
a clock terminal configured to receive a clock signal;
a data clock terminal configured to receive a data clock signal;
a first data terminal configured to receive a first data signal;
a plurality of command/address terminals configured to receive the CBT pattern during the CBT operation, the CBT pattern comprising a plurality of command/address signals;
a plurality of second data terminals configured to receive second data signals, the plurality of second data terminals being in one-to-one correspondence with the command/address signals during the CBT operation; and
a command bus training (CBT) control logic configured to:
determine a logic level of the first data signal in synchronization with the data clock signal and enter into a command bus training (CBT) mode upon determining a first logic level of the first data signal;
determine logic levels of the CBT pattern in synchronization with the clock signal and output the determined CBT pattern through the plurality of second data terminals; and
exit the CBT mode upon determining a second logic level of the first data signal.
12. The memory system of claim 11 , wherein the CBT control logic comprises a comparator to determine logic levels of the CBT pattern by comparing each signal of the CBT pattern with a reference voltage.
13. The memory system of claim 12 , wherein the CBT control logic is further configured to set the level of the reference voltage with a first reference voltage setting code stored in a first mode register.
14. The memory system of claim 13 , wherein the CBT control logic is further configured to receive a second reference voltage setting code through the second data terminals and to change the level of the reference voltage in accordance with the second reference voltage setting code during the CBT mode.
15. The memory system of claim 14 , wherein the CBT control logic is further configured to receive a data mask inversion (DMI) signal, wherein the second reference voltage setting code is determined at rising edge of the DMI signal.
16. The memory system of claim 11 , wherein the memory device further comprising a command/address on-die termination (CA_ODT) control circuit to provide each of the command/address signals with an estimated impedance matching while receiving the CBT pattern, the estimated impedance of the command/address signals being selected from termination resistance values stored in a second mode register.
17. The memory system of claim 16 , wherein the CA_ODT control circuit is configured to perform a frequency set point operation right after entering the CBT mode and before receiving the CBT pattern.
18. The memory system of claim 17 , wherein the frequency set point operation is based on operation frequency of the memory device.
19. The memory system of claim 11 , wherein the memory device further comprising a data clock on-die termination (WCK_ODT) control circuit to provide the data clock signal with a termination based on estimated impedance while determining the logic level of the first data signal.
20. The memory system of claim 11 , wherein the memory device further comprising a data signal on-die termination (DQ_ODT) control circuit which is turned off during the CBT mode, wherein the DQ_ODT control circuit provides the first and second data signals with corresponding termination during a normal write operation.