Memory device to execute read operation using read target voltage
A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
1. A memory device comprising:
a semiconductor substrate having a main surface extending in a first direction and a second direction crossing the first direction,
a bit line provided on a side of the main surface in a third direction crossing the first direction and the second direction and extending the first direction;
a first semiconductor pillar electrically connected to the bit line and extending in the third direction;
a second semiconductor pillar electrically connected to the bit line and extending in the third direction;
a first conductive member extending in the second direction and intersecting the first semiconductor pillar;
a second conductive member extending in the second direction and intersecting the second semiconductor pillar, the first and second conductive members being at a same position in the third direction, the second conductive member being electrically disconnected from the first conductive member;
a plurality of third conductive members arranged between the first conductive member and the semiconductor substrate in the third direction, each of the third conductive members extending in the second direction and intersecting the first semiconductor pillar;
a plurality of fourth conductive members arranged between the second conductive member and the semiconductor substrate in the third direction, each of the fourth conductive members extending in the second direction and intersecting the second semiconductor pillar, the plurality of third conductive members and the plurality of fourth conductive members being at same positions in the third direction, respectively, and electrically connected to each other, respectively;
a fifth conductive member provided between the plurality of third conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the first semiconductor pillar;
a sixth conductive member provided between the plurality of fourth conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the second semiconductor pillar, the fifth and sixth conductive members being at a same position in the third direction;
one or more seventh conductive members provided between the fifth conductive member and the semiconductor substrate in the third direction, each of the one or more seventh conductive members extending in the second direction and intersecting the first semiconductor pillar; and
one or more eighth conductive members provided between the sixth conductive member and the semiconductor substrate in the third direction, each of the one or more eighth conductive members extending in the second direction and intersecting the second semiconductor pillar, the one or more seventh conductive members and the one or more eights conductive members being at same positions in the third direction, respectively, and electrically disconnected to each other, respectively.
2. The memory device according to claim 1 , wherein
each of the first, second, fifth, and sixth conductive members serves as a select gate line, and not a word line, and
each of the third, fourth, seventh, and eighth conductive members serves as a word line.
3. The memory device according to claim 1 , wherein
the first semiconductor pillar includes a first sub pillar extending in the third direction, a second sub pillar extending in the third direction, and a first joint portion provided between the first sub pillar and the third sub pillar,
the second semiconductor pillar includes a third sub pillar extending in the third direction, a fourth sub pillar extending in the third direction, and a second joint portion provided between the third sub pillar and the fourth sub pillar,
the fifth conductive member intersects the first sub pillar,
the sixth conductive member intersects the third sub pillar,
the one or more seventh conductive members intersect the second sub pillar, and
the one or more eighth conductive members intersect the fourth sub pillar.
4. The memory device according to claim 3 , further comprising:
a first charge storage film surrounding the first sub pillar and the second sub pillar; and
a second charge storage film surrounding the third sub pillar and the fourth sub pillar, wherein
the one or more seventh conductive members are a plurality of seventh conductive members,
the one or more eighth conductive members are a plurality of eighths conductive members,
the third conductive members face the first sub pillar via the first charge storage film to forma plurality of first memory cells,
the fourth conductive members face the third sub pillar via the second charge storage film to form a plurality of second memory cells,
the seventh conductive members face the second sub pillar via the first charge storage film to forma plurality of third memory cells, and
the eighth conductive members face the fourth sub pillar via the second charge storage film to form a plurality of fourth memory cells.
5. The memory device according to claim 4 , wherein
each of the third conductive members is electrically connected to a corresponding one of the fourth conductive members via:
a first contact plug extending in the third direction and having one end connected to the third conductive member,
a second contact plug extending in the third direction and having one end connected to the fourth conductive member, and
a first connection portion connected to the other end of the first contact plug and the other end of the second contact plug, and
each of the seventh conductive members is electrically connected to a corresponding one of the eighth conductive members via:
a third contact plug extending in the third direction and having one end connected to the seventh conductive member,
a fourth contact plug extending in the third direction and having one end connected to the eighth conductive member, and
a second connection portion connected to the other end of the third contact plug and the other end of the fourth contact plug.
6. The memory device according to claim 1 , further comprising:
a first charge storage film surrounding the first semiconductor pillar;
a second charge storage film surrounding the second semiconductor pillar;
a third semiconductor pillar electrically connected to the bit line and extending in the third direction through the third conductive members, the fifth conductive member, and the one or more seventh conductive members;
a fourth semiconductor pillar electrically connected to the bit line and extending in the third direction through the fourth conductive members, the sixth conductive member, and the one or more eighth conductive members;
a third charge storage film surrounding the third semiconductor pillar;
a fourth charge storage film surrounding the fourth semiconductor pillar;
a ninth conductive member extending in the second direction and intersecting the third semiconductor pillar, the first and ninth conductive members being at the same position in the third direction, the ninth conductive member being electrically disconnected from the first and second conductive members; and
a tenth conductive member extending in the second direction and intersecting the fourth semiconductor pillar, the first and tenth conductive members at the same position in the third direction, the tenth conductive member being electrically disconnected from the first, second, and ninth conductive members.
7. The memory device according to claim 6 , wherein
the one or more seventh conductive members are a plurality of seventh conductive members, and
the one or more eighth conductive members are a plurality of eighths conductive members,
the memory device further comprising:
an eleventh conductive member provided between the fifth conductive member and the plurality of seventh conductive members in the third direction, extending in the second direction, and intersecting the first semiconductor pillar and the third semiconductor pillar;
a twelfth conductive member provided between the sixth conductive member and the plurality of eighth conductive members in the third direction, extending in the second direction, and intersecting the second semiconductor pillar and the fourth semiconductor pillar, the eleventh and twelfth conductive members being at a same position in the third direction;
a thirteenth conductive member provided between the plurality of seventh conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the first semiconductor pillar and the third semiconductor pillar; and
a fourteenth conductive member provided between the plurality of eighth conductive members and the semiconductor substrate in the third direction, extending in the second direction, and intersecting the second semiconductor pillar and the fourth semiconductor pillar, the thirteenth and fourteenth conductive members being at a same position in the third direction.
8. The memory device according to claim 7 , wherein
each of the first, second, fifth, and sixth, ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth conductive members serves as a select gate line, and not a word line, and
each of the third, fourth, seventh, and eighth conductive members serves as a word line.
9. The memory device according to claim 8 , further comprising:
a first dummy conductive member provided between the fifth conductive member and the eleventh conductive member, extending in the second direction, and intersecting the first semiconductor pillar and the third semiconductor pillar, the first dummy conductive member being not used for any data storage; and
a second dummy conductive member provided between the sixth conductive member and the twelfth conductive member, extending in the second direction, and intersecting the second semiconductor pillar and the fourth semiconductor pillar, the second dummy conductive member being not used for any data storage.
10. The memory device according to claim 1 , further comprising:
a source line electrically connected to an impurity diffusion region provided on the side of the main surface of the semiconductor substrate.