Repair circuit and memory

1. A repair circuit, comprising:

a plurality of redundant memory cells, each of the plurality of redundant memory cells being configured with a state signal; and

a repair component, connected to the plurality of redundant memory cells, and configured to determine target memory cells from the plurality of redundant memory cells based on a plurality of state signals and repair defective memory cells through the target memory cells,

wherein the target memory cells are in one-to-one correspondence to the defective memory cells, the repair component is configured to repair, at each of a plurality of repair stages, a different one or more of the defective memory cells, and the plurality of redundant memory cells are shared at the plurality of repair stages;

wherein the repair component comprises:

a selection circuit, configured to generate unit selection signals according to the plurality of state signals; and

a memory repair circuit, connected to both the selection circuit and the plurality of redundant memory cells, and configured to receive the unit selection signals, determine the target memory cells according to the unit selection signals, and repair the defective memory cells through the target memory cells;

wherein the unit selection signals comprise a plurality of enabling signals which are in one-to-one correspondence to the plurality of redundant memory cells, and at most one of the plurality of enabling signals is enabled at the same time;

wherein the selection circuit comprises a plurality of generation circuits, each of the plurality of generation circuits being configured to generate a respective one of the plurality of enabling signals, and

wherein the memory repair circuit is configured to determine a redundant memory cell corresponding to the enabled enabling signal as a target memory cell.

2. The repair circuit of claim 1 , wherein the selection circuit is configured to generate the unit selection signals according to a preset repair sequence and the plurality of state signals.

3. The repair circuit of claim 1 , wherein the state signal carries occupation information of the redundant memory cell corresponding to the state signal, the occupation information comprises occupation and non-occupation, the selection circuit comprises a first generation circuit configured to generate a first enabling signal and define a redundant memory cell in a first repair sequence as a first redundant memory cell,

wherein when the first redundant memory cell is occupied, the first enabling signal is disabled; and

when the first redundant memory cell is unoccupied, the first enabling signal is enabled.

4. The repair circuit of claim 1 , wherein a redundant memory cell in an n-th repair sequence is defined as an n-th redundant memory cell, n being a positive integer greater than 1, and the selection circuit further comprises an n-th generation circuit configured to generate an n-th enabling signal, wherein

when at least one of all the redundant memory repair circuits in front of the n-th redundant memory cell in the repair sequence is occupied, the n-th enabling signal is disabled; and

when all the redundant memory repair cells in front of the n-th redundant memory cell in the repair sequence are occupied and the n-th redundant memory cell is unoccupied, the n-th enabling signal is disabled.

5. The repair circuit of claim 4 , wherein the n-th generation circuit comprises:

n−1 first logic gates, configured to receive n−1 state signals in a one-to-one correspondence mode, and perform logic operation on the received state signals; and

a second logic gate, configured with n input ends and an output end, wherein the n−1 input ends are connected to the output ends of the n−1 first logic gates in the one-to-one correspondence mode, an input end other than the n−1 input ends is configured to receive an n-th state signal, and the second logic gate is configured to perform logic operation on the plurality of input signals to generate the n-th enabling signal.

6. The repair circuit of claim 5 , wherein the first logic gates are NOT gates, and the second logic gate is an AND gate.

7. The repair circuit of claim 5 , wherein the plurality of generation circuits share at least one of the first logic gates.

8. The repair circuit of claim 1 , wherein the plurality of repair stages comprise a first repair stage and a second repair stage, and the memory repair circuits comprises:

a first repair circuit, connected to both the selection circuit and the plurality of redundant memory cells, and configured to repair the defective memory cells at the first repair stage; and

a second repair circuit, connected to both the selection circuit and the plurality of redundant memory cells, and configured to repair the defective memory cells at the second repair stage;

wherein the first repair stage is earlier than the second repair stage, and the first repair circuit occupies the redundant memory cell prior to the second repair circuit.

9. The repair circuit of claim 8 , wherein the first repair stage is a repair stage after encapsulation, and the second repair stage is a self repair stage.

10. The repair circuit of claim 1 , further comprising:

a detection circuit, connected to the plurality of normal memory cells, and configured to detect operation states of the plurality of normal memory cells, and determine the defective memory cells from the plurality of normal memory cells according to the operation states.

11. The repair circuit of claim 1 , wherein the selection circuit is further configured to receive a repair stage signal input from outside and output the unit selection signals according to the repair stage signal.

12. A memory, comprising:

a plurality of normal memory cells; and

a repair circuit, connected to the plurality of normal memory cells,

wherein the normal memory cells with an abnormal operation state are taken the defective memory cells,

wherein the repair circuit comprises:

a plurality of redundant memory cells, each of the plurality of redundant memory cells being configured with a state signal; and

a repair component, connected to the plurality of redundant memory cells, and configured to determine target memory cells from the plurality of redundant memory cells based on a plurality of state signals and repair defective memory cells through the target memory cells,

wherein the target memory cells are in one-to-one correspondence to the defective memory cells, the repair component is configured to repair, at each of a plurality of repair stages, a different one or more of the defective memory cells, and the plurality of redundant memory cells are shared at the plurality of repair stages;

wherein the repair component comprises:

a selection circuit, configured to generate unit selection signals according to the plurality of state signals; and

a memory repair circuit, connected to both the selection circuit and the plurality of redundant memory cells, and configured to receive the unit selection signals, determine the target memory cells according to the unit selection signals, and repair the defective memory cells through the target memory cells;

wherein the unit selection signals comprise a plurality of enabling signals which are in one-to-one correspondence to the plurality of redundant memory cells, and at most one of the plurality of enabling signals is enabled at the same time;

wherein the selection circuit comprises a plurality of generation circuits, each of the plurality of generation circuits being configured to generate a respective one of the plurality of enabling signals, and

wherein the memory repair circuit is configured to determine a redundant memory cell corresponding to the enabled enabling signal as a target memory cell.

13. The memory of claim 12 , wherein the selection circuit is configured to generate the unit selection signals according to a preset repair sequence and the plurality of state signals.

14. The memory of claim 12 , wherein the state signal carries occupation information of the redundant memory cell corresponding to the state signal, the occupation information comprises occupation and non-occupation, the selection circuit comprises a first generation circuit configured to generate a first enabling signal and define a redundant memory cell in a first repair sequence as a first redundant memory cell,

wherein when the first redundant memory cell is occupied, the first enabling signal is disabled; and

when the first redundant memory cell is unoccupied, the first enabling signal is enabled.

15. The memory of claim 14 , wherein a redundant memory cell in an n-th repair sequence is defined as an n-th redundant memory cell, n being a positive integer greater than 1, and the selection circuit further comprises an n-th generation circuit configured to generate an n-th enabling signal, wherein

when at least one of all the redundant memory repair circuits in front of the n-th redundant memory cell in the repair sequence is occupied, the n-th enabling signal is disabled; and

when all the redundant memory repair cells in front of the n-th redundant memory cell in the repair sequence are occupied and the n-th redundant memory cell is unoccupied, the n-th enabling signal is disabled.

16. The memory of claim 15 , wherein the n-th generation circuit comprises:

n−1 first logic gates, configured to receive n−1 state signals in a one-to-one correspondence mode, and perform logic operation on the received state signals; and

a second logic gate, configured with n input ends and an output end, wherein the n−1 input ends are connected to the output ends of the n−1 first logic gates in the one-to-one correspondence mode, an input end other than the n−1 input ends is configured to receive an n-th state signal, and the second logic gate is configured to perform logic operation on the plurality of input signals to generate the n-th enabling signal.