IP Library › Granted Patent US 11,715,946
Granted Patent B2
US 11,715,946 · App. 17/252,286 · Granted Aug 1, 2023

Electronic device and electrostatic discharge protection circuit

Inventors: Yaobin Guan (Zhuhai, CN); Jianjian Sheng (Zhuhai, CN); Zhenzhe Li (Zhuhai, CN); Junyuan Lv (Zhuhai, CN)
Assignee: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
H02H9/046
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Quick Facts
Patent No.
US 11,715,946
App. No.
17/252,286
Granted
Aug 1, 2023
Kind
B2
Abstract

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

Claims (33)

1. An electronic device, comprising:

a first group III nitride transistor; and

an electrostatic discharge (ESD) protection circuit comprising:

a first transistor having a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor;

a second transistor having a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor; and

a third transistor having a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor; and

a fourth transistor having a drain electrically connected to the gate of the third transistor, a gate electrically connected to the gate of the first group III nitride transistor, and a source electrically connected to the source of the first group III nitride transistor, wherein the first transistor is electrically connected between the gate and drain of the fourth transistor.

2. The electronic device of claim 1 , wherein the ESD protection circuit further comprises:

a first resistor connected between the gate of the third transistor and the drain of the fourth transistor.

3. The electronic device of claim 2 , wherein the drain of the fourth transistor is electrically connected to a drain of the first transistor and wherein the fourth transistor is configured to disconnect the parallel connection between a gate-to-source resistance of the first group III nitride transistor and a series resistance of the first transistor and the first resistor.

4. The electronic device of claim 1 , wherein the ESD protection circuit further comprises:

a fifth transistor having a drain electrically connected to the gate of the third transistor, a gate electrically connected to the source of the first group III nitride transistor, and a source electrically connected to the gate of the first group III nitride transistor.

5. The electronic device of claim 4 , wherein the ESD protection circuit further comprises:

a second resistor connected between the gate of the third transistor and the drain of the fifth transistor.

6. The electronic device of claim 1 , wherein the ESD protection circuit further comprises first N diode-connected transistors electrically connected in series and between the drain of the third transistor and the gate of the third transistor, where N is an integer equal to or greater than 1.

7. The electronic device of claim 6 , wherein the ESD protection circuit is configured to drain a first current from the gate of the first group III nitride transistor if a gate-source voltage applied across the gate and the source of the first group III nitride transistor equals or exceeds a sum of threshold voltages of the first diode-connected transistors and a threshold voltage of the third transistor.

8. The electronic device of claim 6 , wherein the ESD protection circuit further comprises second N diode-connected transistors electrically connected in series and between the source of the third transistor and the gate of the third transistor, where N is an integer equal to or greater than 1.

9. The electronic device of claim 8 , wherein the ESD protection circuit is configured to drain a second current from the source of the first group III nitride transistor if a source-gate voltage applied across the source and the gate of the first group III nitride transistor equals or exceeds a sum of threshold voltages of the second diode-connected transistors and a threshold voltage of the third transistor.

10. The electronic device of claim 1 , wherein the first transistor, the second transistor, and the third transistor include group III nitride transistors.

11. The electronic device of claim 1 , wherein the first group III nitride transistor is a power device.

12. The electronic device of claim 1 , wherein a sum of threshold voltages of the first transistor and the third transistor equals a sum of threshold voltages of the second transistor and the third transistor.

13. An electronic device, comprising:

a first group III nitride transistor; and

an ESD protection circuit comprising:

a first diode having an anode electrically connected to a gate of the first group III nitride transistor;

a second diode having an anode electrically connected to a source of the first group III nitride transistor;

a first transistor having a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the first diode and to a cathode of the second diode, and a source electrically connected to the source of the first group III nitride transistor; and

a second transistor having a drain electrically connected to the gate of the first transistor, a gate electrically connected to the gate of the first group III nitride transistor, and a source electrically connected to the source of the first group III nitride transistor, wherein the first diode is electrically connected between the gate and the drain of the second transistor.

14. The electronic device of claim 13 , wherein the ESD protection circuit further comprises first N diodes electrically connected in series and between the drain of the first transistor and the gate of the first transistor, where N is an integer equal to or greater than 1.

15. The electronic device of claim 14 , wherein the ESD protection circuit is configured to drain a first current from the gate of the first group III nitride transistor if a gate-source voltage applied across the gate and the source of the first group III nitride transistor equals or exceeds a sum of threshold voltages of the first diodes and a threshold voltage of the first transistor.

16. The electronic device of claim 15 , wherein the ESD protection circuit is configured to drain a second current from the source of the first group III nitride transistor if a source-gate voltage applied across the source and the gate of the first group III nitride transistor equals or exceeds a sum of threshold voltages of the second diodes and a threshold voltage of the first transistor.

17. The electronic device of claim 14 , wherein the ESD protection circuit further comprises second N diodes electrically connected in series and between the source of the first transistor and the gate of the first transistor, where N is an integer equal to or greater than 1.

18. The electronic device of claim 13 , wherein a sum of threshold voltages of the first diode and the first transistor equals a sum of threshold voltages of the second diode and the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2020
From: GUAN, YAOBIN; SHENG, JIANJIAN; LI, ZHENZHE; LV, JUNYUAN
To: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
Reel/Frame 054659/0176 →
Continuity (1)
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