Transistor switching based on voltage sensing

1. An apparatus comprising:

a voltage sensing circuit having a voltage sensing terminal and a voltage sensing output, the voltage sensing circuit configured to generate a first voltage at the voltage sensing output representing a second voltage at the voltage sensing terminal;

a control circuit having a control circuit input and a control circuit output, the control circuit input coupled to the voltage sensing output, the control circuit configured to:

determine a state of a transistor based on the first voltage; and

generate a driver signal at the control circuit output based on the state; and

a driver circuit having a driver input and a switch control output, the driver input coupled to the control circuit output, the driver circuit configured to provide a current at the switch control output responsive to the driver signal,

wherein:

the voltage sensing terminal is adapted to be coupled to a current terminal of the transistor;

the switch control output is adapted to be coupled to a control terminal of the transistor; and

the voltage sensing circuit includes a first capacitor and a second capacitor, the first capacitor coupled between the voltage sensing terminal and the voltage sensing output, and the second capacitor adapted to be coupled between the voltage sensing output and a voltage source.

2. The apparatus of claim 1 , further comprising a processing circuit having a processing input and a processing output, the processing input coupled to the voltage sensing output, the processing output coupled to the control circuit input, and the processing circuit including:

a reference generator having a reference output; and

a comparator having a comparator output and first and second comparator inputs, the first comparator input coupled to the processing input, the second comparator input coupled to the reference output, and the comparator output coupled to the processing output, the comparator configured to generate an indication signal at the comparator output responsive to the first voltage at the first comparator input and a reference voltage at the reference output.

3. The apparatus of claim 2 , wherein:

the driver signal is a first driver signal;

the current is a first charge current;

the control circuit is configured to:

generate the first driver signal at the control circuit output responsive to the indication signal indicating that the first voltage exceeds the reference voltage; and

generate a second driver signal at the control circuit output responsive to the indication signal indicating that the first voltage is below the reference voltage; and

the driver circuit is configured to generate first and second charge currents at the switch control output responsive to the respective first and second driver signals to charge the control terminal.

4. The apparatus of claim 2 , wherein:

the driver signal is a first driver signal;

the current is a charge current;

the control circuit input is a first control circuit input;

the control circuit has a second control circuit input, the control circuit configured to:

receive a switching signal at the second control circuit input;

generate the first driver signal responsive to the switching signal having a first state; and

generate a second driver signal responsive to the switching signal having a second state; and

the driver circuit is configured to:

generate a discharge current at the switch control output responsive to the first driver signal to discharge the control terminal; and

generate a charge current at the switch control output responsive to the second driver signal to charge the control terminal.

5. The apparatus of claim 4 , further comprising a delay circuit having a delay output and a delay input, the delay input coupled to the second control circuit input;

wherein:

the discharge current is a first discharge current;

the comparator has a timing input coupled to the delay output, and the comparator is configured to generate the indication signal responsive to a transition of the switching signal at the timing input;

the control circuit is configured to generate a third driver signal responsive to the indication signal indicating that the first voltage exceeds the reference voltage; and

the driver circuit is configured to generate a second discharge current to discharge the control terminal responsive to the third driver signal.

6. The apparatus of claim 5 , wherein the second discharge current is less than the first discharge current.

7. The apparatus of claim 5 , wherein:

the reference voltage is a first reference voltage;

the reference generator has a reference selection input and is configured to:

provide the first reference voltage at the reference output responsive to a first selection signal at the reference selection input; and

provide a second reference voltage at the reference output responsive to a second selection signal at the reference selection input, the second reference voltage being lower than the first reference voltage; and

the control circuit has a reference selection output coupled to the reference selection input, and the control circuit is configured to:

provide the first selection signal at the reference selection output;

responsive to the indication signal indicating that the first voltage does not exceed the first reference voltage, provide the second selection signal at the reference selection output; and

generate the third driver signal responsive to the indication signal indicating that the first voltage exceeds the second reference voltage.

8. The apparatus of claim 3 , wherein the control circuit is configured to generate the first and second driver signals in respective first and second phases of enabling of the transistor, the second phase being preceded by the first phase.

9. The apparatus of claim 8 , wherein the first charge current is higher than the second charge current.

10. The apparatus of claim 9 , wherein:

the control circuit is configured to generate a third driver signal at the control circuit output in a third phase of enabling of the transistor, and the third phase is preceded by the first and second phases; and

the driver circuit is configured to generate a third charge current at the switch control output to charge the control terminal responsive to the third driver signal, the third charge current being higher than the first and second charge current.

11. The apparatus of claim 8 , wherein the control circuit is configured to:

in a first feedback loop:

generate a first comparison result responsive to a comparison between: a first target rate; and a rate of change of the first voltage introduced by the first driver signal; and

adjust the first driver signal based on the first comparison result; and

in a second feedback loop:

generate a second comparison result responsive to a comparison between: a second target rate; and a rate of change of the first voltage introduced by the second driver signal; and

adjust the second driver signal based on the second comparison result.

12. The apparatus of claim 11 , wherein the voltage sensing circuit includes:

a differentiator circuit having a differentiator input and a differentiator output, the differentiator input coupled to the voltage sensing terminal;

a peak detector having a detector input and a detector output, the detector input coupled to the differentiator output;

a bias buffer having a bias output; and

an amplifier having a first amplifier input, a second amplifier input, a first amplifier output, and a second amplifier output, the first amplifier input coupled to the detector output, the second amplifier input coupled to the bias output, and the first and second amplifiers output coupled to the voltage sensing output, the amplifier configured to provide a pair of differential voltage signals at the first and second amplifier outputs, the pair of differential voltage signals representing a voltage difference between the detector output and the bias output.

13. The apparatus of claim 12 , wherein:

the reference output is a first reference output;

the reference generator has a second and third reference outputs;

the comparator is a first comparator, the first comparator input of the first comparator is coupled to the first and second amplifier outputs, and the second comparator input of the first comparator is coupled to the first and second reference outputs;

the comparator output is a first comparator output;

the processing output is a first processing output;

the indication signal is a first indication signal;

the processing circuit has a second processing output and includes:

a second comparator having a second comparator output and third and fourth comparator inputs, the third comparator input coupled to the first and second amplifier outputs, the fourth comparator input coupled to the first and third reference outputs, and the second comparator output coupled to the second processing output;

the first comparator is configured to provide the first indication signal at the first comparator output to indicate whether the rate of change of the first voltage is below a first target rate; and

the second comparator is configured to provide a second indication signal at the second comparator output to indicate whether the rate of change of the first voltage is above a second target rate higher than the first target rate.

14. The apparatus of claim 11 , wherein:

the reference output is a first reference output;

the reference generator has a second reference output;

the comparator is a first comparator;

the comparator output is a first comparator output;

the processing circuit further includes:

a second comparator having a third comparator input coupled to the processing input, a fourth comparator input coupled to the second reference output, and a second comparator output;

a counter having a start input, and end input, and a count output, the start input coupled to the first comparator output, and the end input coupled to the second comparator output; and

a count processor having a count input and an indication output, the count input coupled to the count output, the indication output coupled to the processing output, and the count processor configured to provide the indication signal based on comparing a count value at the count input with a count threshold representing a target rate.

15. A method comprising:

receiving a switching signal;

responsive to the switching signal having a first state, providing a first discharge current at a control terminal of a transistor;

responsive to the switching signal transitioning from the first state to a second state, providing a first charge current at the control terminal;

receiving a first voltage representing a second voltage of a current terminal of the transistor when providing the first charge current;

performing a comparison between the first voltage and a first threshold;

responsive to the first voltage being below the threshold, providing a second charge current at the control terminal of the transistor;

responsive to a pre-determined time having elapsed from the transition, performing a comparison between the first voltage and a second threshold; and

responsive to the first voltage exceeding the second threshold, providing a second discharge current at the control terminal, the second discharge current being lower than the first discharge current.

16. The method of claim 15 , wherein the second charge current is lower than the first charge current.

17. The method of claim 15 , further comprising:

responsive to the first voltage being below the second threshold, and the switching signal having the second state, performing a comparison between the first voltage and a third threshold, the third threshold being below the second threshold; and

responsive to the first voltage exceeding the third threshold, providing the second discharge current at the control terminal.

18. The method of claim 15 , further comprising:

in a first feedback loop:

generating a first comparison result responsive to a comparison between: a first target rate; and a rate of change of the first voltage introduced by the first charge current; and

adjusting the first charge current based on the first comparison result; and

in a second feedback loop:

generating a second comparison result responsive to a comparison between: a second target rate; and a rate of change of the first voltage introduced by the second charge current; and

adjusting the second charge current based on the second comparison result.