Device and method for multi-link operations

1. A device comprising:

a processor configured to:

perform a first backoff operation on a first link and a second backoff operation on a second link of a multi-link device (MLD) that has a non-simultaneous transmission and reception capability (NSTR MLD); and

transmit a first Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) on the first link at a first start time after the first backoff operation and a second PPDU on the second link at a second start time after the second backoff operation.

2. The device of claim 1 , wherein a difference between the first start time and the second start time is no more than a Receive-Transmit Turnaround Time (aRxTxTurnaroundTime).

3. The device of claim 1 , wherein a difference between the first start time and the second start time is no more than 4 microseconds (p).

4. The device of claim 1 , wherein a first backoff counter of the first backoff operation becomes zero after a first backoff counter of the second backoff operation and a second backoff counter of the second backoff operation have become zero.

5. The device of claim 4 , wherein the first backoff counter of the second backoff operation and the second backoff counter of the second backoff operation become zero at different times.

6. The device of claim 4 , wherein the first backoff counter of the second backoff operation and the second backoff counter of the second backoff operation become zero at a same time.

7. The device of claim 1 , wherein the first PPDU includes a first Aggregated-Media Access Control (MAC) Protocol Data Unit (MPDU) (A-MPDU) with frames from a first Access Category (AC), and the second PPDU includes a second A-MPDU with frames from a second AC.

8. The device of claim 7 , wherein the processor is configured to perform another backoff operation on the second link for an AC that is not included in the second PPDU, and wherein a Contention Window (CW) of the AC (CW[AC]) and a Quality of Service (QoS) Short Reply Counter (QSRC) of the AC (QSRC[AC]) are unchanged.

9. The device of claim 7 , wherein the processor is configured to perform another backoff operation on the second link for an AC that is not included in the second PPDU after a QSRC[AC] is increased by one and a CW[AC] is doubled.

10. The device of claim 9 , wherein the CW[AC] is doubled if the CW[AC] is less than a max CW of the AC (CWmax[AC]).

11. The device of claim 9 , wherein the CW[AC] is set to a minimum CW of the AC (CWmin[AC]) if the QSRC[AC] reaches a threshold value.

12. The device of claim 1 , wherein a first backoff counter of the first backoff operation becomes zero after a first backoff counter of the second backoff operation and a second backoff counter of the second backoff operation have become zero; and

wherein the first PPDU includes a first A-MPDU with frames from a first AC and the second PPDU includes a second A-MPDU with frames from a second AC.

13. The device of claim 12 , wherein the second A-MPDU with frames from the second AC corresponds to at least one of the first backoff counter of the second backoff operation and the second backoff counter of the second backoff operation.

14. The device of claim 1 , wherein the processor is configured to perform another backoff operation on the second link once a backoff counter on the first link becomes zero to break a deadlock that occurs after the first backoff operation and the second backoff operation.

15. The device of claim 1 , wherein the processor is configured to perform another backoff operation on the second link once the second link becomes idle to break a deadlock that occurs after the first backoff operation and the second backoff operation.

16. The device of claim 1 , wherein the first backoff operation includes a backoff counter for a corresponding AC and the second backoff operation includes another backoff counter for another corresponding AC.

17. The device of claim 1 , wherein the device includes:

a first station (STA), STA 1 , that performs the first backoff operation on the first link; and

a second STA, STA 2 , that performs the second backoff operation on the second link.

18. The device of claim 1 , wherein the processor is configured to operate according to an Institute of Electrical and Electronics Engineers (IEEE) 802.11be communication protocol.

19. A method of multi-link operations, the method comprising:

performing, by a multi-link device (MLD) that has a non-simultaneous transmission and reception capability (NSTR MLD), a first backoff operation on a first link and a second backoff operation on a second link; and

transmitting, by the NSTR MLD, a first Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) on the first link at a first start time after the first backoff operation and a second PPDU on the second link at a second start time after the second backoff operation.

20. A method of multi-link operations, the method comprising:

performing, by a multi-link device (MLD) that has a non-simultaneous transmission and reception capability (NSTR MLD), a first backoff operation on a first link and a second backoff operation on a second link, wherein performing the first backoff operation and the second backoff operation includes:

a first station (STA), STA 1 , performing the first backoff operation on the first link; and

a second STA, STA 2 , performing the second backoff operation on the second link; and

transmitting, by STA 1 and STA 2 , a first Physical Layer Convergence Protocol (PLCP) Protocol Data Unit (PPDU) on the first link at a first start time after the first backoff operation and a second PPDU on the second link at a second start time after the second backoff operation.