Semiconductor device and method for forming the wiring structures avoiding short circuit thereof

1. An apparatus comprising:

a memory cell region;

a peripheral region adjacent to the memory cell region;

first, second, third, fourth and fifth bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and

first, second and third bit-line contacts connecting with the first, third and fifth bit-lines in the peripheral region, respectively;

wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween; and

wherein the second and third bit-line contacts are arranged adjacently with interposing the fourth bit-line therebetween.

2. The apparatus of claim 1 , wherein first distance between the first bit-line contact and the second bit-line contact is shorter than second distance between the second bit-line contact and the third bit-line contact.

3. The apparatus of claim 1 , wherein the first, second, third, fourth and fifth bit-lines are arranged with a predetermined repeating pitch.

4. The apparatus of claim 1 , wherein a center of width of the first bit-line contact is shifted from a center of width of the first bit-line and a center of width of the second bit-line contact is shifted from a center of width of the third bit-line.

5. The apparatus of claim 1 , wherein the center of width of the first bit-line contact is shifted from the center of width of the first bit-line in a first direction and the center of width of the second bit-line contact is shifted from the center of width of the third bit-line in a second direction opposite to the first direction.

6. The apparatus of claim 5 , wherein the center of width of the third bit-line contact is shifted from the center of width of the fifth bit-line in the first direction.

7. The apparatus of claim 1 , wherein the first, second, third, fourth and fifth bit-lines include at least either tungsten or titanium nitride.

8. The apparatus of claim 1 , wherein the first, second and third bit-line contacts include tungsten.

9. An apparatus comprising:

a memory cell region;

a peripheral region adjacent to the memory cell region;

first, second and third bit-lines arranged in numerical order and extending across the memory cell region and the peripheral region; and

first and second bit-line contacts connecting with the first and third bit-lines in the peripheral region, respectively;

wherein a center of width of the first bit-line contact is shifted from a center of width of the first bit-line and a center of width of the second bit-line contact is shifted from a center of width of the third bit-line.

10. The apparatus of claim 9 , wherein the center of width of the first bit-line contact is shifted from the center of width of the first bit-line in a first direction and the center of width of the second bit-line contact is shifted from the center of width of the third bit-line in a second direction opposite to the first direction.

11. The apparatus of claim 9 , wherein the centers of widths of the first and second bit-line contacts are shifted such that the first and second bit-line contacts get close to each other.

12. The apparatus of claim 9 , wherein the first, second and third bit-lines are arranged with a predetermined repeating pitch.

13. The apparatus of claim 9 , wherein the first and second bit-line contacts are arranged adjacently without interposing the second bit-line therebetween.

14. The apparatus of claim 9 , wherein a length of each of the first and third bit-lines is longer than a length of the second bit-line in the peripheral region.

15. The apparatus of claim 9 , wherein the first, second and third bit-lines include at least either tungsten or titanium nitride.

16. The apparatus of claim 9 , wherein the first and second bit-line contacts include tungsten.