Managing a mode to access a memory component or a logic component for machine learning computation in a memory sub-system
A system can include a memory device with an array of memory cells and a machine learning operation component. The machine learning operation component can perform a machine learning computation in association with the array of memory cells. The system can also include a processing device that is operatively coupled with the memory device to perform operations that include setting the memory device to a first mode based on a first mode setting signal received from a host system, where in the first mode, the processing device exposes the array of memory cells to the host system and routes input data from the host system to the array of memory cells. The operations can also include, setting the memory device to a second mode, where in the second mode, the processing device exposes the machine learning operation component to the host system.
1. A system comprising:
a memory device comprising an array of memory cells and a machine learning operation component, the machine learning operation component to perform a machine learning computation in association with the array of memory cells; and
a processing device, operatively coupled with the memory device to perform operations comprising:
setting the memory device to a first mode based on a first mode setting signal received from a host system, wherein in the first mode, the processing device exposes the array of memory cells to the host system and routes input data from the host system to the array of memory cells; and
responsive to receiving a second mode setting signal, setting the memory device to a second mode, wherein in the second mode, the processing device exposes the machine learning operation component to the host system.
2. The system of claim 1 , wherein the memory device further comprises:
a mode selection component that provides a mode selection signal to indicate either the first mode or second mode for the memory device; and
a decoding component coupled with the mode selection component, the decoding component to enable the host system to access the array of memory cells or the machine learning operation component based on the mode selection signal from the mode selection component.
3. The system of claim 2 , wherein setting the system to the first mode based on the first mode setting signal comprises causing the mode selection component to provide a first mode selection signal based on the first mode setting signal to the decoding component, wherein the first mode selection signal represents the first mode, and the decoding component enables the host system to access the array of memory cells based on the first mode selection signal selecting the first mode; and
wherein setting the system to the second mode based on the second mode setting signal comprises:
causing the mode selection component to provide a second mode selection signal based on the second mode setting signal to the decoding component, wherein the second mode selection signal represents the second mode, and the decoding component enables the host system to access the machine learning operation component based on the second mode selection signal.
4. The system of claim 3 , wherein the mode selection component includes a mode register.
5. The system of claim 4 , wherein the first mode setting signal and second mode setting signal each correspond to respective mode register setting (MRS) commands.
6. The system of claim 3 , wherein the mode selection component includes an input pin dedicated for mode selection and the memory device further includes a pull up resistor and a switch that are coupled to the input pin.
7. The system of claim 6 , wherein:
the first mode setting signal corresponds to a switch control signal to open the switch causing a voltage signal having a voltage level satisfying a threshold condition to be provided to the input pin as the first mode selection signal; and
the second mode setting signal corresponds to a switch control signal to close the switch causing a voltage signal having a voltage level not satisfying the threshold condition to be provided to the input pin as the second mode selection signal.
8. A non-transitory computer readable storage medium comprising instructions that, when executed by a processing device operatively coupled with a memory device, cause the processing device to perform operations comprising:
setting the memory device to a first mode based on a first mode setting signal received from a host system, wherein the memory device includes an array of memory cells and a machine learning operation component, the machine learning operation component to perform a machine learning computation in association with the array of memory cells and wherein in the first mode, the processing device exposes the array of memory cells to the host system; and
responsive to receiving a second mode setting signal, setting the memory device to a second mode wherein in the second mode, the processing device exposes the machine learning operation component to the host system and routes an execution signal from the host system to the machine learning operation component.
9. The non-transitory computer readable storage medium of claim 8 , wherein the memory device further includes:
a mode selection component that provides a mode selection signal to indicate either the first mode or second mode for the memory device; and
a decoding component coupled with the mode selection component, the decoding component to enable the host system to access the array of memory cells or the machine learning operation component based on the mode selection signal from the mode selection component.
10. The non-transitory computer readable storage medium of claim 9 , wherein:
setting the memory device to the first mode based on the first mode setting signal comprises causing the mode selection component to provide a first mode selection signal based on the first mode setting signal to the decoding component, wherein the first mode selection signal represents the first mode, and the decoding component enables the host system to access the array of memory cells based on the first mode selection signal selecting the first mode; and
setting the memory device to the second mode based on the second mode setting signal comprises causing the mode selection component to provide a second mode selection signal based on the second mode setting signal to the decoding component, wherein the second mode selection signal represents the second mode, and the decoding component enables the host system to access the machine learning operation component based on the second mode selection signal.
11. The non-transitory computer readable storage medium of claim 10 , wherein the mode selection component includes a mode register.
12. The non-transitory computer readable storage medium of claim 11 , wherein the first mode setting signal and second mode setting signal each correspond to respective mode register setting (MRS) commands.
13. The non-transitory computer readable storage medium of claim 10 , wherein the mode selection component includes an input pin dedicated for mode selection and the memory device further includes a pull up resistor and a switch that are coupled to the input pin.
14. The non-transitory computer readable storage medium of claim 13 , wherein:
the first mode setting signal corresponds to a switch control signal to open the switch causing a voltage signal having a voltage level satisfying a threshold condition to be provided to the input pin as the first mode selection signal; and
the second mode setting signal corresponds to a switch control signal to close the switch causing a voltage signal having a voltage level not satisfying the threshold condition to be provided to the input pin as the second mode selection signal.
15. A system comprising:
a memory device comprising an array of memory cells and a machine learning operation component, the machine learning operation component to perform a machine learning computation in association with the array of memory cells; and
a processing device, operatively coupled with the memory device to perform operations comprising:
responsive to receiving a mode setting signal indicating a mode selected from a first mode and a second mode, causing the memory device to operate in a corresponding mode, wherein:
in the first mode, the processing device is to receive input data for the machine learning computation from a host system and route the input data to one or more memory cells in the array of memory cells of the memory device; and
in the second mode, the processing device is to receive an execution signal to perform the machine learning computation from the host system and route the execution signal to the machine learning operation component of the memory device.
16. The system of claim 15 , wherein the execution signal indicates a type of model and the input data to be used for the machine learning computation.
17. The system of claim 16 , wherein in the second mode, the processing device is to perform the operations further comprising:
providing a corresponding address of the type of model and the input data stored in one or more memory cells of the array of memory cells to the machine learning operation component.
18. The system of claim 15 , wherein in the second mode, the processing device is to perform the operations further comprising:
responsive to detecting that the machine learning operation component has generated output data from the machine learning computation, providing the output data to the host system.
19. The system of claim 15 , wherein the mode setting signal indicating the first mode and the mode setting signal indicating the second mode each respectively cause one of two voltage signals having different voltage levels to be supplied to the memory device.
20. The system of claim 15 , wherein the mode setting signal indicating the first mode and the mode setting signal indicating the second mode respectively correspond to different mode register setting (MRS) commands.