IP Library › Granted Patent US 11,720,487
Granted Patent B2
US 11,720,487 · App. 17/500,465 · Granted Aug 8, 2023

Memory system and method of controlling nonvolatile memory

Inventor: Shinichi Kanno (Ota, JP)
Assignee: Kioxia Corporation
G06F12/0246G06F12/1009G06F13/1673G11C16/08G11C16/26G06F2212/7201
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Quick Facts
Patent No.
US 11,720,487
App. No.
17/500,465
Granted
Aug 8, 2023
Kind
B2
Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.

Claims (31)

1. An information processing system comprising:

a host including a submission queue and a completion queue; and

a memory system connected to the host,

the memory system comprising:

a nonvolatile memory including a plurality of blocks each including a plurality of pages; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is configured to:

in response to receiving a first write command from the host through the submission queue of the host, determine a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and update an address translation table such that the first physical address is associated with a logical address of the first write data; and

transfer the first write data from a write buffer in a memory of the host to the controller, and write the first write data to a write destination location in a first write destination block of the nonvolatile memory, which is designated by the first physical address,

the controller is configured to start updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.

2. The information processing system of claim 1 , wherein

the nonvolatile memory is configured to enable read of data written to one page of a plurality of pages in each block to be executed after writing data to one or more pages subsequent with the page,

the controller is configured to:

in response to receiving a read command from the submission queue of the host, acquire a second physical address corresponding to a logical address of read target data designated by the read command from the address translation table; and

when the second physical address is indicative of a physical storage location which is not readable in the first write destination block, read the read target data from a buffer, based on information indicative of a location in the buffer where data which is being written to or waiting for being written to each physical address not readable in the first write destination block is stored, and

the buffer is a first buffer in the memory system or the write buffer of the host.

3. The information processing system of claim 1 , wherein

the nonvolatile memory is configured to enable read of data written to one page of a plurality of pages in each block to be executed after writing data to one or more pages subsequent with the page, and

the controller is configured to:

manage, with respect to each of a plurality of write destination blocks allocated from the plurality of blocks, a pointer indicative of a minimum physical address of an un-readable area from which data is un-readable, and manage, with respect to each of blocks where data are already written to all pages, a physical address larger than a physical address of a block end as the pointer;

acquire a second physical address corresponding to a logical address of read target data designated by the read command from the address translation table, the second physical address including a block address indicative of a read target block and an offset indicative of a read target location in the read target block; and

read the read target data from the read target block when the offset is smaller than a value of a pointer corresponding to the read target block, and read the read target data from a buffer when the offset is larger than or equal to the value of the pointer corresponding to the read target block, the buffer being a first buffer in the memory system or the write buffer of the host.

4. The information processing system of claim 3 , wherein

the controller is configured to:

manage, with respect to each of the write destination blocks, buffer management information indicative of correspondence between each of physical addresses of an un-readable area and each of locations in the buffer where data which are being written to or waiting for being written to the physical address are stored;

acquire a location in the buffer where the read target data is stored, by referring to buffer management information corresponding to the read target block; and

read the read target data from the acquired location in the buffer.

5. The information processing system of claim 1 , wherein

the controller is configured to return a response indicative of completion of the first write command to the host by storing the response in the completion queue of the host when updating the address translation table is finished and when transfer of the first write data is finished, or when updating the address translation table is finished and when write of the first write data to the nonvolatile memory is finished.

6. The information processing system of claim 1 , wherein

the controller is configured to return, to the host, a response indicating that the first write command is received when updating the address translation table is finished.

Priority Claims (1)
JP 2019-155834 · Aug 28, 2019 · national
Continuity (2)
Continuation 16815894 · Mar 11, 2020
Related Publication 20220100651A1 · Mar 31, 2022