Semiconductor package and method of fabricating the same

1. A semiconductor package, comprising:

a package substrate;

a first interposer substrate mounted on the package substrate;

a second interposer substrate disposed on the first interposer substrate; and

a semiconductor chip mounted on the second interposer substrate,

wherein the first interposer substrate comprises:

a first base layer;

a second base layer disposed on the first base layer, a top surface of the first base layer contacting a bottom surface of the second base layer;

a first pad exposed with respect to the first base layer at the top surface of the first base layer and connected to a first interconnection pattern which is in the first base layer;

a second pad exposed with respect to the second base layer at the bottom surface of the second base layer; and

a third pad exposed with respect to the second base layer at a top surface of the second base layer,

wherein the first pad and the second pad are connected to each other, at an interface between the first base layer and the second base layer,

wherein a second interconnection pattern of the second interposer substrate is connected to the third pad, at an interface between the second base layer of the first interposer substrate and the second interposer substrate, and

wherein the first base layer and the second base layer are each formed of silicon (si).

2. The semiconductor package of claim 1 , wherein the first pad and the second pad constitute a single body formed of the same material as each other.

3. The semiconductor package of claim 2 , wherein the first pad and the second pad comprise a metallic material.

4. The semiconductor package of claim 1 , wherein each of the second pad and the third pad are portions of a through electrode vertically penetrating the second base layer.

5. The semiconductor package of claim 4 , wherein an aspect ratio of the through electrode is a ratio in a range from 0.1 to 2.0.

6. The semiconductor package of claim 1 , wherein the third pad and the second interconnection pattern of the second interposer substrate constitute a single body formed of the same metal material.

7. The semiconductor package of claim 1 , wherein the second interposer substrate is one of a plurality of second interposer substrates, and

the semiconductor chip is disposed, such that a portion thereof overlaps two of the second interposer substrates in a plan view, and is electrically connected to each of the two second interposer substrates.

8. The semiconductor package of claim 1 , further comprising an integrated circuit device embedded in the first base layer and connected to the first interconnection pattern,

wherein the integrated circuit device is a capacitor or an active device.

9. The semiconductor package of claim 8 , wherein the integrated circuit device comprises a first conductive layer and a second conductive layer, which extend horizontally and are vertically spaced apart from each other in the first base layer, and an insulating layer provided between the first conductive layer and the second conductive layer, and

the first conductive layer and the second conductive layer are parts of the first interconnection pattern.

10. The semiconductor package of claim 1 , wherein the semiconductor chip is mounted on the second interposer substrate through a chip terminal which is disposed between the semiconductor chip and a pad of the second interposer substrate.

11. The semiconductor package of claim 1 , wherein the first interposer substrate further comprises connection terminals, which are disposed on a bottom surface of the first base layer and are electrically connected to the first interconnection pattern, and

the first interposer substrate is mounted on the package substrate through the connection terminals.

12. The semiconductor package of claim 1 , further comprising a heat sink disposed on a top surface of the semiconductor chip.

13. A semiconductor package, comprising:

a package substrate;

a first interposer substrate mounted on the package substrate, the first interposer substrate comprising a first sub-interposer substrate and a second sub-interposer substrate that contact each other;

a second interposer substrate disposed on the first interposer substrate; and

a semiconductor chip mounted on the second interposer substrate,

wherein:

the first sub-interposer substrate comprises a first interconnection pattern provided therein,

the second sub-interposer substrate comprises a bottom pad and a top pad, which are connected to each other through a via penetrating the second sub-interposer substrate,

at an interface between the first sub-interposer substrate and the second sub-interposer substrate, the first interconnection pattern and the bottom pad constitute a single body formed of the same material as each other, and

a top surface of the first interposer substrate and a bottom surface of the second interposer substrate contact each other and are coplanar with each other.

14. The semiconductor package of claim 13 , wherein the first interconnection pattern and the bottom pad of the second sub-interposer substrate are formed to constitute a continuous body, in which an interface between the first interconnection pattern and the bottom pad is absent.

15. The semiconductor package of claim 13 , wherein the second interposer substrate comprises a second interconnection pattern provided therein,

the second interconnection pattern and the top pad of the second sub-interposer substrate are formed to constitute a continuous body, in which an interface between the second interconnection pattern and the top pad is absent.

16. The semiconductor package of claim 13 , wherein the first sub-interposer substrate further comprises an integrated device, which is provided therein and is electrically connected to the first interconnection pattern.

17. The semiconductor package of claim 13 , wherein the top pad and the bottom pad comprise a metallic material.

18. The semiconductor package of claim 13 , wherein an aspect ratio of the via is a ratio in a range from 0.1 to 2.0.

19. The semiconductor package of claim 13 , wherein the first sub-interposer substrate and the second sub-interposer substrate are each formed of silicon (Si).