Transistor structure and method of forming thereof

1. A transistor comprising:

a semiconductor drain region delimited by three sides of a first trench;

a first electrically conductive element located in the first trench; and

a first node electrically coupled to the first electrically conductive element, the first node configured to be coupled to a first potential closer to a drain potential of the transistor than to a source potential of the transistor.

2. The transistor of claim 1 , further comprising a gate located in a second trench collinear with the first trench.

3. The transistor of claim 2 , further comprising, between the gate and the first electrically conductive element, an insulating region having a first thickness greater than a second thickness of a gate insulator of the transistor.

4. The transistor of claim 2 , further comprising a second conductive element located in the second trench.

5. The transistor of claim 1 , wherein the first trench extends into a substrate from a surface of the substrate, and wherein a drain contacting area of the transistor and a channel-forming area of the transistor are located on a side of the surface of the substrate.

6. The transistor of claim 5 , wherein the channel-forming area is electrically coupled to a second node configured to be coupled to the source potential of the transistor.

7. The transistor of claim 5 , further comprising:

a gate located in a second trench collinear with the first trench; and

a semiconductor source region delimited by the second trench, and in contact with the channel-forming area on a side of the channel-forming area opposite to the semiconductor drain region.

8. The transistor of claim 5 , wherein the first trench extends into a region of the substrate partly located under the semiconductor drain region.

9. The transistor of claim 8 , wherein the channel-forming area is a portion of the region of the substrate.

10. The transistor of claim 8 , wherein the region of the substrate is insulated, by a buried well, from another region of the substrate located under the buried well.

11. The transistor of claim 10 , wherein the buried well is entirely located at a depth greater than that of a bottom of the first trench.

12. The transistor of claim 1 , wherein the semiconductor drain region is delimited, on a side opposite to that of the first trench, by an additional trench, and wherein an additional electrically conductive element is located in the additional trench.

13. The transistor of claim 12 , wherein ends of the first trench and of the additional trench are aligned in a trench width direction.

14. The transistor of claim 1 , wherein the semiconductor drain region has, in a direction parallel to the first trench, a decreasing doping level from a contacting area.

15. An electronic device comprising:

one or more transistors, each of the one or more transistors comprising:

a semiconductor drain region delimited by three sides of a first trench;

a first electrically conductive element located in the first trench; and

a first node electrically coupled to the first electrically conductive element, the first node configured to be coupled to a first potential closer to a drain potential of the transistor than to a source potential of the transistor.

16. The electronic device of claim 15 , wherein the electronic device is monolithic and further comprises:

complementary metal-oxide-semiconductor (CMOS)-type transistors, and/or a vertical transistor comprising trenches of a same depth as the first trench.

17. A method of forming a transistor, the method comprising:

forming a buried well in a semiconductor substrate;

etching first and second trenches in the substrate to a depth shallower than the buried well, the first and second trenches collinear with and spaced apart from each other;

conformally depositing an electrically insulating layer on bottoms and sidewalls of the first and second trenches, and on a surface of the substrate;

filling the first and second trenches with an electrically conductive material, thereby forming first and second electrically conductive elements, respectively;

etching portions of the electrically insulating layer and the electrically conductive material over and partially into a section of the second trench;

forming a gate insulator on the electrically insulating layer, the electrically conductive material and the sidewalls of the second trench, in the section of the second trench;

depositing a gate on the gate insulator in the section of the second trench;

doping a first section of substrate adjacent to the first trench to form a semiconductor drain region, the semiconductor drain region delimited by three sides of the first trench;

doping a second section of substrate, on a side of the second trench opposite to the first section of the substrate, to form a semiconductor source region;

forming a first drift region in the semiconductor drain region; and

electrically coupling the first drift region to the first electrically conductive element.

18. The method of claim 17 , further comprising:

etching a third trench in the substrate delimiting the semiconductor drain region on a side of the semiconductor drain region opposite to the first trench;

conformally depositing the electrically insulating layer on a bottom and sidewalls of the third trench;

filling the third trench with the electrically conductive material, thereby forming a third electrically conductive element in the third trench; and

electrically coupling the third electrically conductive element to the first electrically conductive element.

19. The method of claim 17 , further comprising, before the etching the portions of the electrically insulating layer and the electrically conductive material:

forming a mask having an opening exposing the section of the second trench, the mask opening having a strip shape with an elongation direction orthogonal to the collinear first and second trenches.

20. The method of claim 17 , further comprising forming a second drift region in the semiconductor source region.