Semiconductor device and manufacturing method thereof

1. A method, comprising:

forming a source/drain region on a substrate;

forming a dielectric layer over the source/drain region;

forming a contact hole in the dielectric layer;

forming a contact hole liner in the contact hole;

removing a first portion of the contact hole liner to expose a sidewall of the contact hole in a first etching step, wherein the first etching step also removes a portion of the contact hole liner to expose the source/drain region;

performing a second etching step to recess the source/drain region, wherein the second etching step also etches the exposed sidewall of the contact hole to laterally expand the contact hole; and

forming a contact plug in the laterally expanded contact hole.

2. The method of claim 1 , wherein after the removing the first portion of the contact hole liner, a second portion of the contact hole liner in a position lower than the exposed sidewall of the contact hole remains in the contact hole.

3. The method of claim 2 , wherein after the etching the exposed sidewall of the contact hole to laterally expand the contact hole, the second portion of the contact hole liner remains in the contact hole.

4. The method of claim 3 , wherein the laterally expanded contact hole has an upper sidewall non-parallel with the second portion of the contact hole liner.

5. The method of claim 3 , wherein the second portion of the contact hole liner has a steeper slope than an upper sidewall of the laterally expanded contact hole.

6. The method of claim 1 , wherein the contact plug fills a recess in the recessed source/drain region.

7. The method of claim 1 , wherein the contact plug has a stepped sidewall structure comprising a lower sidewall contacting a remaining portion of the contact hole liner, an upper sidewall laterally set back from the lower sidewall and contacting a sidewall of the laterally expanded contact hole, and an intermediary surface extending from a bottom end of the upper sidewall to a top end of the lower sidewall.

8. The method of claim 7 , further comprising:

forming a gate structure adjacent to the source/drain region, wherein the intermediary surface of the stepped sidewall structure of the contact plug meets a top end of the contact hole liner at a position higher than a top surface of the gate structure.

9. The method of claim 1 , wherein the step of etching the exposed sidewall of the contact hole to laterally expand the contact hole is performed after the source/drain region is exposed.

10. The method of claim 1 , wherein the contact hole liner comprises a nitride material.

11. A method, comprising:

forming a semiconductor fin protruding from a substrate;

forming a gate structure and source/drain epitaxy structures over the semiconductor fin;

depositing an inter-layer dielectric (ILD) structure over the source/drain epitaxy structures;

performing a first etching process to form a first contact hole extending through the ILD structure down to a first one of the source/drain epitaxy structures;

depositing a liner layer lining a bottom surface and sidewalls of the first contact hole;

performing a second etching process to remove the liner layer from the bottom surface of the first contact hole, such that the first one of the source/drain epitaxy structures is exposed in the first contact hole;

after performing the second etching process, performing a third etching process to recess the first one of the source/drain epitaxy structures, wherein the third etching process also results in laterally expanding the first contact hole; and

forming a first source/drain contact extending through the first contact hole to the recessed first one of the source/drain epitaxy structures.

12. The method of claim 11 , further comprising:

after performing the second etching process and before performing the third etching process, performing a plasma ashing process on the source/drain epitaxy structures.

13. The method of claim 10 , wherein the ILD structure comprises a lower ILD layer and an upper ILD layer over the lower ILD layer, and after performing the second etching process, the liner layer has a top end lower than a top surface of the upper ILD layer but higher than a top surface of the lower ILD layer.

14. The method of claim 10 , wherein the first etching process also results in a second contact hole extending through the ILD structure down to a second one of the source/drain epitaxy structures, the liner layer also lines a bottom surface and sidewalls of the second contact hole, and the second etching process also removes the liner layer from the bottom surface of the second contact hole such that the second one of the source/drain epitaxy structures is exposed in the second contact hole.

15. The method of claim 14 , wherein the third etching process also recesses the second one of the source/drain epitaxy structures.

16. The method of claim 15 , further comprising:

forming a second source/drain contact extending through the second contact hole to the recessed second one of the source/drain epitaxy structures.

17. A method, comprising:

forming a gate structure and source/drain epitaxy structures over a semiconductor fin;

depositing a first ILD layer over the source/drain epitaxy structures;

planarizing the first ILD layer and the gate structure;

depositing a second ILD layer over the planarized first ILD layer;

etching a contact hole through the first and second ILD layers to expose a first one of the source/drain epitaxy structures;

depositing a liner layer in the contact hole and over the first one of the source/drain epitaxy structures;

etching the liner layer to expose the first one of the source/drain epitaxy structures again by using an etching step, wherein the etching step of etching the liner layer leaves a polymer on the first one of the source/drain epitaxy structures, and the etching step enlarges a width of the contact hole;

performing a plasma ashing process to remove the polymer from the first one of the source/drain epitaxy structures; and

after removing the polymer from the first one of the source/drain epitaxy structures, forming a source/drain contact in the contact hole.

18. The method of claim 17 , further comprising:

after performing the plasma ashing process and before forming the source/drain contact, performing an etching process to form a recess in the first one of the source/drain epitaxy structures.

19. The method of claim 18 , wherein the etching process also form a recess in a second one of the source/drain epitaxy structures.

20. The method of claim 17 , wherein etching the liner layer results in a remainder of the liner layer has a top end above an interface between the first and second ILD layers.