Chip, private key generation method, and trusted certification method

1. A chip comprising:

an external module; and

a security core module comprising:

a memory configured to:

store a first hash of a first root public key and a unique device secret (UDS) of the chip, and

store a layer 1 private key; and

a security core configured to generate a layer 1 public key and the layer 1 private key based on the first hash,

wherein the security core module is configured to prevent access to itself by the external module and by an external device outside the chip.

2. The chip of claim 1 , wherein the security core module comprises an address outside an address range that is accessible by the external module and the external device.

3. The chip of claim 2 , wherein the memory is further configured to:

store a second hash of a second root public key; and

store a layer 2 private key,

wherein the security core is further configured to:

generate a layer 2 public key and a layer 2 private key based on the second hash; and

sign a layer 2 certificate using the layer 1 private key,

wherein the layer 2 certificate comprises the layer 2 public key.

4. The chip of claim 2 , wherein the security core is further configured to:

receive verification request information from a challenge device;

run, in response to the verification request information, secure firmware to sign target data based on the layer 1 private key in order to create signed target data; and

send the signed target data to the challenge device to prompt the challenge device to verify the signed target data based on the layer 1 public key.

5. The chip of claim 1 , wherein the memory is further configured to:

store a second hash of a second root public key; and

store a layer 2 private key,

wherein the security core is further configured to:

generate a layer 2 public key and a layer 2 private key based on the second hash, and

sign a layer 2 certificate using the layer 1 private key,

wherein the layer 2 certificate comprises the layer 2 public key.

6. The chip of claim 5 , wherein the security core is further configured to:

sign the layer 2 certificate using the layer 1 private key; and

delete the layer 1 private key after the signing.

7. The chip of claim 6 , wherein the security core is further configured to:

receive verification request information from a challenge device;

run, in response to the verification request information, secure firmware to sign target data based on the layer 2 private key in order to create signed target data; and

send the signed target data to the challenge device to prompt the challenge device to verify the signed target data based on the layer 2 public key.

8. The chip of claim 5 , wherein the security core is further configured to:

receive verification request information from a challenge device;

run, in response to the verification request information, secure firmware to sign target data based on the layer 2 private key in order to create signed target data; and

send the signed target data to the challenge device to prompt the challenge device to verify the signed target data based on the layer 2 public key.

9. The chip according to claim 1 , wherein the security core is further configured to:

receive verification request information from a challenge device;

run, in response to the verification request information, secure firmware to sign target data based on the layer 1 private key in order to create signed target data; and

send the signed target data to the challenge device to prompt the challenge device to verify the signed target data based on the layer 1 public key.

10. The chip of claim 1 , further comprising a service core configured to run service core firmware.

11. The chip of claim 10 , further comprising:

a first input/output (I/O) interface coupled to the security core module; and

a second I/O interface coupled to the service core.

12. A method comprising:

storing, by a memory of a security core module of a chip, a first hash of a first root public key and a unique device secret (UDS) of the chip;

generating, by a security core of the security core module, a layer 1 public key and a layer 1 private key based on the first hash;

storing, by the memory, the layer 1 private key; and

preventing, by the security core module, access to itself by an external module of the chip and by an external device outside the chip.

13. The method of claim 12 , further comprising:

storing, by the memory, a second hash of a second root public key and the UDS;

generating, by the security core, a layer 2 public key and a layer 2 private key based on the second hash;

storing, by the memory, the layer 2 private key; and

signing, by the security core, a layer 2 certificate using the layer 1 private key,

wherein the layer 2 certificate comprises the layer 2 public key.

14. The method of claim 13 , further comprising:

signing, by the security core, the layer 2 certificate using the layer 1 private key; and

deleting, by the security core after the signing, the layer 1 private key.

15. The method of claim 13 , further comprising:

obtaining, by the security core from a challenge device, verification request information;

running, by the security core in response to the verification request information, secure firmware to sign target data based on the layer 2 private key in order to create signed target data; and

sending, by the security core to the challenge device, the signed target data to prompt the challenge device to verify the signed target data based on the layer 2 public key.

16. The method of claim 12 , further comprising:

obtaining, by the security core from a challenge device, verification request information;

running, by the security core in response to the verification request information, secure firmware to sign target data based on the layer 1 private key in order to create signed target data; and

sending, by the security core to the challenge device, the signed target data to prompt the challenge device to verify the signed target data based on the layer 1 public key.