IP Library › Granted Patent US 11,722,688
Granted Patent B2
US 11,722,688 · App. 17/674,488 · Granted Aug 8, 2023

Block size restrictions for DMVR

Inventors: Hongbin Liu (Beijing, CN); Li Zhang (San Diego, CA); Kai Zhang (San Diego, CA); Yue Wang (Beijing, CN)
Assignees: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD; BYTEDANCE INC.
H04N19/513H04N19/176H04N19/44H04N19/56
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Quick Facts
Patent No.
US 11,722,688
App. No.
17/674,488
Granted
Aug 8, 2023
Kind
B2
Abstract

Methods of enabling and disabling a decoder-side motion vector refinement (DMVR) video decoder and/or encoder are described. One example method includes determining a width (W) and a height (H) of a video block, making a determination, based on a condition of the video block, between enabling and disabling a decoder side motion vector refinement step for a conversion between the video block and a coded representation of the video block, in a case that the determination is enabling, performing the conversion by enabling the decoder side motion vector refinement step; and in a case that the determination is disabling, performing the conversion by disabling the decoder side motion vector refinement step, wherein the decoder side motion vector refinement step includes refining value of a motion vector signaled in the coded representation and using the refined value during the conversion.

Claims (46)

1. A method of video processing, comprising:

performing a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block;

refraining from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and

refraining from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion,

wherein W and H are the width and the height of the video block, respectively,

wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, and

wherein the decoder side motion vector refinement step is applied in a sub-block level.

2. The method of claim 1 , wherein the conversion includes decoding the bitstream into pixel values of the video block.

3. The method of claim 1 , wherein the conversion includes encoding pixel values of the video block into the bitstream.

4. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

5. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 and H<=T2.

6. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W*H<=T0, wherein T0 is a fifth threshold and T0 is an integer value greater than or equal to 1.

7. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 and H=4.

8. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 or H=4.

9. The method of claim 1 , wherein the first threshold value and the second threshold value have fixed values.

10. The method of claim 1 , wherein the second threshold value is equal to 8; and

wherein in response to an affine mode being applied to the current block, the decoder side motion vector refinement step is refrained from the current block.

11. An apparatus for coding video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:

perform a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block;

refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and

refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion,

wherein W and H are the width and the height of the video block, respectively,

wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, and

wherein the decoder side motion vector refinement step is applied in a sub-block level.

12. The apparatus of claim 11 , wherein the conversion includes decoding the bitstream into pixel values of the video block.

13. The apparatus of claim 11 , wherein the conversion includes encoding pixel values of the video block into the bitstream.

14. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

15. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 and H<=T2.

16. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W*H<=T0, wherein T0 is a fifth threshold and T0 is an integer value greater than or equal to 1.

17. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 and H=4.

18. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 or H=4.

19. A non-transitory computer-readable storage medium storing instructions that cause a processor to:

perform a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block;

refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and

refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion,

wherein W and H are the width and the height of the video block, respectively,

wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion,

wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4, and

wherein the decoder side motion vector refinement step is applied in a sub-block level.

20. A non-transitory computer-readable storage medium storing a bitstream of a video which is generated by a method performed by a video processing apparatus, wherein the method comprises:

generating the bitstream based on at least one of a width and a height of the video block;

refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and

refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion,

wherein W and H are the width and the height of the video block, respectively,

wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, and

wherein the decoder side motion vector refinement step is applied in a sub-block level.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2022
From: ZHANG, LI; ZHANG, KAI
To: BYTEDANCE INC.
Reel/Frame 059041/0187 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2022
From: LIU, HONGBIN; WANG, YUE
To: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
Reel/Frame 059041/0229 →
Continuity (4)
Continuation 16998653 · Aug 20, 2020
Continuation PCTIB2019055616 · Jul 2, 2019
Provisional Application 62693412 · Jul 2, 2018
Related Publication 20220174309A1 · Jun 2, 2022
Cited By (1)
US 12,238,330