STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance
View Patent ↗An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.
1. A device comprising:
a first magnetic tunneling junction (MTJ) stack;
a first encapsulation layer disposed directly on sidewall surfaces of the first MTJ stack;
a first heat shield layer disposed directly on the first encapsulation layer along the sidewall surfaces of the first MTJ stack;
a first magnetic shield layer disposed directly on the first heat shield layer along the sidewall surfaces and directly on a top surface of the first MTJ stack;
a bit line disposed directly on the first magnetic shield layer such that the first magnetic shield layer prevents the bit line from interfacing with the top surface of the first MTJ stack; and
an interlayer dielectric fill layer extending continuously from a bottom surface of the bit line to a top surface of the first encapsulation layer, the top surface of the first encapsulation layer facing the bottom surface of the bit line.
2. The device of claim 1 , wherein the interlayer dielectric fill layer physically contacts the bit line, the first magnetic shield layer, the first heat shield layer and the first encapsulation layer.
3. The device of claim 1 , further comprising:
a second MTJ stack spaced apart from the first MTJ stack;
the first encapsulation extending continuously from the first MTJ stack to the second MTJ stack, the first encapsulation layer disposed directly on sidewall surfaces of the second MTJ stack;
a second heat shield layer disposed directly on the first encapsulation layer along the sidewall surfaces of the second MTJ stack;
a second magnetic shield layer disposed directly on the second heat shield layer along the sidewall surfaces and directly on a top surface of the second MTJ stack;
the bit line extending continuously from the first magnetic shield layer to the second magnetic shield layer, the bit line disposed directly on the second magnetic shield layer such that the second magnetic shield layer prevents the bit line from interfacing with the top surface of the second MTJ stack.
4. The device of claim 3 , wherein the first heat shield layer is spaced apart and separated away from the second shield layer, and
wherein the first magnetic shield layer is spaced apart and separated away from the second magnetic shield layer.
5. The device of claim 4 , wherein the first and second heat shield layers are formed of the same material, and
wherein the first and second magnetic shield layers are formed of the same material.
6. The device of claim 1 , wherein the first encapsulation layer is formed of a material selected from the group consisting of SiN, SiO 2 , Al 2 O 3 and MgO,
wherein the first heat shield layer is formed of a material selected from the group consisting of Ti, TiN, Cu, Ta, TaN, W, Al and AN, and
wherein the first magnetic shield layer is formed of a material selected from the group consisting of NiFe and CoFe.
7. The device of claim 1 , wherein the first encapsulation layer has a top surface and the first heat shield layer has a top surface, and
wherein the top surface of the first MTJ stack is at the same level as the top surfaces of the first encapsulation layer and the first heat shield layer.
8. The device of claim 7 , wherein the first magnetic shield layer physically contacts the top surfaces of the first encapsulation layer and the first heat shield layer.
9. A device comprising:
a multiplicity of separate patterned magnetic tunneling junction (MTJ) stacks, wherein each MTJ stack is encapsulated by a configuration of four sequentially formed layers, wherein said sequence of four layers comprises:
a first layer that protects each said stack from oxidation;
a second layer that conformally contacts said first layer and that serves as a heat sink layer;
a third layer that conformally contacts said second layer and serves as a magnetic shield;
a fourth layer that is a hard mask layer that has been used to pattern said second and third layers; and
an interlayer dielectric material filling spaces between and surrounding each said patterned MTJ stacks, and
a continuous BIT line that physically contacts an exposed upper surface of each MTJ stack and exposed upper surfaces of the first, second, third and fourth layers that are respectively encapsulating each MTJ stack.
10. The device of claim 9 , wherein the first layer is a layer of SiN, SiO 2 , AlO, AlN or MgO formed to a thickness between approximately 20-200 A.
11. The device of claim 9 , wherein the second layer is a material chosen from the group consisting of Ti, TiN, Cu, Ta, TaN, W, Al and AlN, and wherein the second layer has a thickness between approximately 20-100 A.
12. The device of claim 9 , wherein the interlayer dielectric material is SiO 2 or SiN formed to a thickness between approximately 20-200 A.
13. The device of claim 9 , wherein the fourth layer is a layer of SiO 2 or SiN formed to a thickness between approximately 50-300 A.
14. The device of claim 9 , wherein the third layer is a material having magnetic permeability chosen from NiFe or CoFe formed to a thickness between approximately 20-100 A.
15. The device of claim 9 , wherein the second layer is chosen to have a coefficient of thermal expansion that provides stress relief during device operation.
16. The device of claim 9 , wherein the interlayer dielectric material physically contacts at least first layer and the second layer.
17. A device comprising:
a first magnetic tunneling junction (MTJ) stack;
a first encapsulation layer disposed directly on sidewall surfaces of the first MTJ stack;
a first heat shield layer disposed directly on the first encapsulation layer along the sidewall surfaces of the first MTJ stack;
a second encapsulation layer disposed directly on sidewall surfaces of the first heat shield layer;
an interlayer dielectric layer disposed directly on the first encapsulation layer, the heat shield layer and the second encapsulation layer such that the interlayer dielectric layer physically contacts the first encapsulation layer, the heat shield layer and the second encapsulation layer; and
a bit line disposed over the interlayer dielectric layer and electrically coupled to the first MTJ stack.
18. The device of claim 17 , further comprising
a second MTJ stack spaced apart from the first MTJ stack;
the first encapsulation extending continuously from the first MTJ stack to the second MTJ stack, the first encapsulation layer disposed directly on sidewall surfaces of the second MTJ stack; and
the bit line electrically coupled to the second MTJ stack and extending continuously from over the first MTJ stack to over the second MTJ stack to electrically couple the second MTJ stack to the first MTJ stack.
19. The device of claim 17 , wherein a respective top surface of each of the first MTJ stack, the first encapsulation layer, the first heat shield layer and the second encapsulation layer physically contact the bit line.
20. The device of claim 17 , wherein the first heat shield layer is formed of a material selected from the group consisting of Ti, TiN, Cu, Ta, TaN, W, Al and AN.