Apparatus and method for executing recurrent neural network and LSTM computations

1. An apparatus for backward pass in a recurrent neural network (RNN) network, comprising:

one or more slave computation circuits configured to calculate:

a first cell output partial sum based on a first portion of a weight vector of the RNN network and an output difference of a current computation period and

a second cell output partial sum based on a second portion of the weight vector of the RNN network and an output difference of a next computation period; and

an interconnection circuit configured to add the first cell output partial sum and the second cell output partial sum to generate one or more cell output gradients;

a master computation circuit configured to activate a dormant output gate value with a derivative of an activation function to generate an activated output gate value,

wherein the one or more slave computation circuits are configured to multiply the cell output gradients with activated current cell status to generate a cell output multiplication result,

wherein the master computation circuit is further configured to multiply the activated output gate value with the cell output multiplication result to generate one or more output gate gradients,

wherein the one or more slave computation circuits are configured to calculate a first cell status partial sum, a second cell status partial sum, a third cell status partial sum, a fourth cell status partial sum, and a fifth cell status partial sum, and

wherein the interconnection circuit is configured to add the first cell status partial sum, the second cell status partial sum, the third cell status partial sum, the fourth cell status partial sum, and the fifth cell status partial sum to generate one or more cell status gradients.

2. The apparatus of claim 1 , wherein the master computation circuit is configured to:

activate a cell input of the current computation period to generate one or more activated cell input; and

multiply an activated input gate value, the activated cell input, with the cell status gradients to generate one or more cell input gradients.

3. The apparatus of claim 2 ,

wherein the one or more slave computation circuits configured to multiply the cell status gradients with a previous cell status of the previous computation period to generate a forget gate multiplication result;

wherein the master computation circuit is configured to:

activate a dormant forget gate value to generate an activated forget gate value; and

multiply the activated forget gate value with the forget gate multiplication result to generate one or more forget gate gradients.

4. The apparatus of claim 2 ,

wherein the master computation circuit is configured to

activate a current cell status of the current computation period to generate an activated current cell status, and

activate the dormant input gate value to generate an activated input gate value;

wherein the one or more slave computation circuits are configured to multiply the activated current cell status with the one or more cell status gradients to generate an input gate multiplication result; and

wherein the master computation circuit is further configured to multiply the activated input gate value with the input gate multiplication result to generate one or more input gate gradients.

5. A method for backward pass in a recurrent neural network (RNN) network, comprising:

calculating, by one or more slave computation circuits,

a first cell output partial sum based on a first portion of a weight vector of the RNN network and an output difference of a current computation period, and

a second cell output partial sum based on a second portion of the weight vector of the RNN network and an output difference of a next computation period;

adding, by an interconnection circuit, the first cell output partial sum and the second cell output partial sum to generate one or more cell output gradients;

activating, by a master computation circuit, a dormant output gate value with a derivative of an activation function to generate an activated output gate value;

multiplying, by the one or more slave computation circuits, the cell output gradients with activated current cell status to generate a cell output multiplication result,

multiplying, by the master computation circuit, the activated output gate value with the cell output multiplication result to generate one or more output gate gradients;

calculating, by the one or more slave computation circuits, a first cell status partial sum, a second cell status partial sum, a third cell status partial sum, a fourth cell status partial sum, and a fifth cell status partial sum; and

adding, by the interconnection circuit, the first cell status partial sum, the second cell status partial sum, the third cell status partial sum, the fourth cell status partial sum, and the fifth cell status partial sum to generate one or more cell status gradients.

6. The method of claim 5 , further comprising:

activating, by the master computation circuit, a cell input of a current computation period to generate one or more activated cell input; and

multiplying, by the master computation circuit, an activated input gate value, the activated cell input, with the cell status gradients to generate one or more cell input gradients.

7. The method of claim 6 , further comprising:

multiplying, by the one or more slave computation circuits, the cell status gradients with a previous cell status of a previous computation period to generate a forget gate multiplication result;

activating, by the master computation circuit, a dormant forget gate value to generate an activated forget gate value;

multiplying, by the master computation circuit, the activated forget gate value with the forget gate multiplication result to generate one or more forget gate gradients.

8. The method of claim 6 , further comprising:

activating, by the master computation circuit, a current cell status of the current computation period to generate an activated current cell status;

activating, by the master computation circuit, the dormant input gate value to generate an activated input gate value;

multiplying, by the one or more slave computation circuits, the activated current cell status with the one or more cell status gradients to generate an input gate multiplication result; and

multiplying, by the master computation circuit, the activated input gate value with the input gate multiplication result to generate one or more input gate gradients.