IP Library › Granted Patent US 11,728,173
Granted Patent B2
US 11,728,173 · App. 17/038,499 · Granted Aug 15, 2023

Masking layer with post treatment

Inventors: Wen-Ju Chen (Taipei, TW); Chung-Ting Ko (Kaohsiung, TW); Wan-Chen Hsieh (Hsinchu, TW); Chun-Ming Lung (Hsinchu, TW); Tai-Chun Huang (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/3085H01L21/0234H01L21/02348H01L21/02356H01L21/02521H01L21/02529H01L21/02532H01L21/02603H01L21/3065H01L21/3086H01L21/31111H01L21/823807H01L21/823814H01L21/823828H01L21/823864H01L21/823871H01L27/092H01L29/0673H01L29/41733H01L29/42392H01L29/66545H01L29/66553H01L29/66636H01L29/66742H01L29/78618H01L29/78696
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Quick Facts
Patent No.
US 11,728,173
App. No.
17/038,499
Granted
Aug 15, 2023
Kind
B2
Abstract

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Claims (48)

1. A method, comprising:

forming a semiconductor layer over a substrate;

etching a portion of the semiconductor layer to form a first recess and a second recess;

forming a first masking layer over the semiconductor layer;

performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer, wherein after the first thermal treatment, the first masking layer has a rougher upper surface than before the first thermal treatment;

etching the first masking layer to expose the first recess;

forming a first semiconductor material in the first recess; and

removing the first masking layer.

2. The method of claim 1 , wherein the first semiconductor material comprises at least one of silicon germanium, silicon carbide, phosphorous doped silicon carbide, and silicon phosphide.

3. The method of claim 1 , wherein the performing the first thermal treatment comprises a radiation treatment.

4. The method of claim 1 , wherein the performing the first thermal treatment comprises a plasma treatment.

5. The method of claim 1 , wherein the first thermal treatment crystallizes at least a portion of the first masking layer.

6. The method of claim 1 further comprising:

forming a second masking layer over the semiconductor layer;

performing a second thermal treatment on the second masking layer, the second thermal treatment densifying the second masking layer;

etching the second masking layer to expose the second recess; and

forming a second semiconductor material in the second recess.

7. The method of claim 6 , wherein one of the first thermal treatment and the second thermal treatment further comprises a plasma treatment.

8. A method, comprising:

forming a semiconductor layer over a first substrate; etching the semiconductor layer to form a first recess in a first region and a second recess in a second region;

depositing a first masking layer over the first region and the second region;

increasing the surface roughness of the first masking layer by performing at least one of a thermal treatment or a plasma treatment;

removing the first masking layer from the second region;

forming a first epitaxial source/drain region in the second recess;

removing a remainder of the first masking layer;

depositing a second masking layer over the first region and the second region;

increasing the surface roughness of the second masking layer;

removing the second masking layer from the first region;

forming a second epitaxial source/drain region in the first recess;

removing a remainder of the second masking layer; and

forming a gate structure over the semiconductor layer.

9. The method of claim 8 , wherein the increasing the surface roughness of the first masking layer comprises performing the thermal treatment on the first masking layer.

10. The method of claim 9 , wherein the performing the thermal treatment on the first masking layer is performed at a temperature of greater than 650° C.

11. The method of claim 8 , wherein the first masking layer comprises a metal oxide.

12. The method of claim 8 , wherein one of the increasing the surface roughness of the first masking layer and the increasing the surface roughness of the second masking layer comprises performing the thermal treatment, and wherein the other comprises performing the plasma treatment.

13. The method of claim 12 , wherein one of the increasing the surface roughness of the first masking layer and the increasing the surface roughness of the second masking layer further comprises performing a UV radiation treatment.

14. The method of claim 8 , wherein before the increasing the surface roughness of the first masking layer, the first masking layer is amorphous, and wherein after the increasing the surface roughness of the first masking layer, at least an upper portion of the first masking layer is crystalline.

15. The method of claim 8 , wherein the removing the remainder of the first masking layer comprises a wet etch using hydrofluoric acid.

16. A method, comprising:

depositing a masking layer over a substrate, the substrate comprising a first recess and a second recess;

performing a post-deposition treatment on the masking layer to crystallize at least a portion of the masking layer;

after performing the post-deposition treatment on the masking layer, anisotropically etching the masking layer to expose the second recess;

epitaxially growing a first portion of a semiconductor material over the masking layer and a second portion of the semiconductor material in the second recess, the first portion comprising discontinuous nodules; and

isotropically etching to remove the masking layer.

17. The method of claim 16 , wherein the performing the post-deposition treatment comprises performing a thermal treatment.

18. The method of claim 17 , wherein the performing the post-deposition treatment further comprises performing a plasma treatment.

19. The method of claim 18 , wherein the post-deposition treatment further comprises a UV treatment.

20. The method of claim 16 , wherein after performing the post-deposition treatment, an exposed surface of the masking layer is rougher than before performing the post-deposition treatment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2020
From: CHEN, WEN-JU; KO, CHUNG-TING; HSIEH, WAN-CHEN; LUNG, CHUN-MING; HUANG, TAI-CHUN; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054643/0609 →
Continuity (1)
Related Publication 20220102152A1 · Mar 31, 2022
Cited By (1)
US 12,328,929