Semiconductor device and semiconductor package including penetration via structure

1. A semiconductor device, comprising:

a semiconductor substrate having a first surface and a second surface, which are opposite to each other;

an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region;

a power rail electrically connected to the source/drain region;

a power delivery network disposed on the second surface of the semiconductor substrate;

a device isolation layer disposed on the first surface of the semiconductor substrate and covering a side surface of the active pattern,

wherein the power rail is buried in the device isolation layer; and

a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network,

wherein the penetration via structure comprises:

a first conductive pattern electrically connected to the power rail; and

a second conductive pattern electrically connected to the power delivery network,

wherein the first conductive pattern comprises a material different from the second conductive pattern.

2. The semiconductor device of claim 1 , wherein the penetration via structure further comprises:

a barrier pattern interposed between the semiconductor substrate and the first conductive pattern and between the semiconductor substrate and the second conductive pattern.

3. The semiconductor device of claim 2 , wherein the penetration via structure further comprises:

a seed pattern interposed between the barrier pattern and the second conductive pattern,

wherein the seed pattern comprises a same material as the first conductive pattern.

4. The semiconductor device of claim 3 , wherein the seed pattern and the first conductive pattern are in direct contact with each other and form a single object.

5. The semiconductor device of claim 2 , wherein the penetration via structure further comprises:

a seed pattern interposed between the barrier pattern and the first conductive pattern and between the barrier pattern and the second conductive pattern,

wherein the seed pattern comprises a material different from the first conductive pattern.

6. The semiconductor device of claim 5 , wherein the first conductive pattern comprises an extended portion interposed between the seed pattern and the second conductive pattern.

7. The semiconductor device of claim 5 , wherein the seed pattern comprises a same material as the second conductive pattern.

8. The semiconductor device of claim 5 , wherein the seed pattern comprises a material different from the second conductive pattern.

9. The semiconductor device of claim 2 , wherein the penetration via structure further comprises:

an insulating pattern interposed between the semiconductor substrate and the barrier pattern.

10. The semiconductor device of claim 1 , wherein the power delivery network comprises:

a plurality of lower interconnection lines disposed on the second surface of the semiconductor substrate,

wherein the second conductive pattern of the penetration via structure penetrates a portion of the semiconductor substrate and is connected to a corresponding one of the lower interconnection lines.

11. The semiconductor device of claim 10 ,

wherein

the first conductive pattern of the penetration via structure penetrates another portion of the semiconductor substrate and is electrically connected to the power rail.

12. The semiconductor device of claim 11 , further comprising:

a first contact disposed on the first surface of the semiconductor substrate and electrically connected to the source/drain region,

wherein the first contact comprises a contact extended portion penetrating the device isolation layer and connected to the power rail.

13. The semiconductor device of claim 10 , further comprising:

a first contact disposed on the first surface of the semiconductor substrate and electrically connected to the source/drain region;

a plurality of upper interconnection lines disposed on the first contact; and

a plurality of upper vias disposed between the first contact and the upper interconnection lines,

wherein the power rail is located at a same height as the upper interconnection lines, from the first surface of the semiconductor substrate, and

the first contact is electrically connected to the power rail through a corresponding one of the upper vias.

14. A semiconductor device, comprising:

a semiconductor substrate having a first surface and a second surface, which are opposite to each other;

a transistor disposed on the first surface of the semiconductor substrate;

a power rail electrically connected to a terminal of the transistor;

a lower insulating layer disposed on the second surface of the semiconductor substrate;

a plurality of lower interconnection lines disposed in the lower insulating layer; and

a penetration via structure penetrating the semiconductor substrate and electrically connecting a corresponding one of the lower interconnection lines to the power rail,

wherein the penetration via structure extends from the second surface toward the first surface in a direction substantially perpendicular to the second surface of the semiconductor substrate, and

the penetration via structure comprises:

a first conductive pattern electrically connected to the power rail; and

a second conductive pattern electrically connected to the corresponding lower interconnection line,

wherein the first conductive pattern comprises a first metal, and the second conductive pattern comprises a second metal different from the first metal.

15. The semiconductor device of claim 14 , wherein the penetration via structure further comprises:

a barrier pattern interposed between the semiconductor substrate and the first conductive pattern and between the semiconductor substrate and the second conductive pattern; and

an insulating pattern interposed between the semiconductor substrate and the barrier pattern.

16. The semiconductor device of claim 15 , wherein the penetration via structure further comprises:

a seed pattern interposed between the barrier pattern and the first conductive pattern and between the barrier pattern and the second conductive pattern.

17. The semiconductor device of claim 16 , wherein the seed pattern comprises a same metal as the first conductive pattern or the second conductive pattern.

18. The semiconductor device of claim 16 , wherein the seed pattern comprises a metal different from the first and second conductive patterns.

19. The semiconductor device of claim 16 , wherein the first conductive pattern comprises an extended portion interposed between the seed pattern and the second conductive pattern.

20. A semiconductor package, comprising:

a lower semiconductor chip including a semiconductor substrate and a penetration via structure penetrating the semiconductor substrate; and

an upper semiconductor chip disposed on the lower semiconductor chip,

wherein the upper semiconductor chip is electrically connected to the lower semiconductor chip through the penetration via structure, and

the penetration via structure comprises:

a first conductive pattern penetrating a lower portion of the semiconductor substrate; and

a second conductive pattern penetrating an upper portion of the semiconductor substrate;

a barrier pattern interposed between the semiconductor substrate and the first conductive pattern and between the semiconductor substrate and the second conductive pattern;

an insulating pattern interposed between the semiconductor substrate and the barrier pattern; and

a seed pattern interposed between the barrier pattern and the first conductive pattern and between the barrier pattern and the second conductive pattern,

wherein the first conductive pattern comprises a first metal, and the second conductive pattern comprises a second metal different from the first metal.