Semiconductor device

1. A semiconductor device comprising:

a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on another side;

an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including:

a second-conductivity-type body region formed in a surface layer portion of the first main surface,

a first-conductivity-type emitter region formed in a surface layer portion of the body region, and

a gate electrode facing both the body region and the emitter region across a gate insulating layer;

a diode region that includes:

a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface, and

a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface;

a boundary region that includes a second-conductivity-type well region formed in the surface layer portion of the first main surface in a region between the IGBT region and the diode region;

a first main surface electrode that is electrically connected to the emitter region, to the first impurity region, and to the well region on the first main surface; and

a trench formed on the first main surface divides the diode region and the boundary region,

wherein one end of the trench is in contact with the diode region, and a part of another end of the trench is in contact with only the second-conductivity-type well region of the boundary region in a cross-section.

2. The semiconductor device according to claim 1 , further comprising:

a second main surface electrode that is electrically connected to the collector region and to the second impurity region on the second main surface.

3. The semiconductor device according to claim 1 , wherein the boundary region includes the well region formed in a region that overlaps the collector region in plan view.

4. The semiconductor device according to claim 1 , wherein the boundary region includes the well region formed in a region that does not overlap the second impurity region in plan view.

5. The semiconductor device according to claim 1 , wherein the boundary region includes a boundary FET structure formed in a region adjoining the well region in the first main surface, the boundary FET structure including:

a second-conductivity-type boundary body region formed in the surface layer portion of the first main surface,

a first-conductivity-type boundary emitter region formed in a surface layer portion of the boundary body region, and

a boundary gate electrode facing both the boundary body region and the boundary emitter region across a boundary gate insulating layer.

6. The semiconductor device according to claim 5 , wherein

a plurality of the well regions are formed in the surface layer portion of the first main surface, and

the boundary FET structure is formed in a region between the plurality of well regions in the surface layer portion of the first main surface.

7. The semiconductor device according to claim 5 , wherein the well region is divided from the boundary FET structure by a region separation trench formed in the first main surface.

8. The semiconductor device according to claim 5 , wherein the IGBT region includes a second-conductivity-type floating region formed such as to adjoin the FET structure in the surface layer portion of the first main surface.

9. The semiconductor device according to claim 8 , wherein the IGBT region includes:

a plurality of the FET structures formed with an interval between the FET structures; and

the floating region formed in a region between the plurality of FET structures in the surface layer portion of the first main surface.

10. The semiconductor device according to claim 8 , wherein the floating region is electrically separated from the first main surface electrode.

11. The semiconductor device according to claim 8 , wherein the gate electrode faces the body region and the emitter region across the gate insulating layer in a gate trench formed in the first main surface.

12. The semiconductor device according to claim 8 , wherein the floating region is divided from the FET structure by a region separation trench formed in the first main surface.

13. The semiconductor device according to claim 1 , wherein the IGBT region includes a second-conductivity-type floating region formed such as to adjoin the FET structure in the surface layer portion of the first main surface.

14. The semiconductor device according to claim 13 , wherein the IGBT region includes:

a plurality of the FET structures formed with intervals between the FET structures; and

the floating region formed in a region between the plurality of FET structures in the surface layer portion of the first main surface.

15. The semiconductor device according to claim 13 , wherein the floating region is electrically separated from the first main surface electrode.

16. The semiconductor device according to claim 13 , wherein the gate electrode faces the body region and the emitter region across the gate insulating layer in a gate trench formed in the first main surface.

17. The semiconductor device according to claim 13 , wherein the floating region is divided from the FET structure by a region separation trench formed in the first main surface.

18. The semiconductor device according to claim 1 , wherein the IGBT region, the boundary region, the diode region, the boundary region, and the IGBT region are formed in this order along a one-way direction in plan view.

19. The semiconductor device according to claim 1 , wherein the diode region, the boundary region, the IGBT region, the boundary region, and the diode region are formed in this order along a one-way direction in plan view.