Multi-gate metal-oxide-semiconductor field effect transistor
A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
1. A semiconductor device, comprising:
a substrate;
a fin protruding from the substrate;
a plurality of nanosheets disposed on the fin;
a gate disposed on the fin, the gate including a main gate portion on the plurality of nanosheets, and a plurality of sub-gate portions between the plurality of nanosheets and the fin;
a source/drain disposed on the fin, an outer edge region of an upper surface of the source/drain being higher in vertical position relative to an inner region thereof; and
a plurality of insulating spacers disposed on sidewalls of the plurality of sub-gate portions,
wherein:
the plurality of sub-gate portions include a first sub-gate portion, and a second sub-gate portion disposed above the first sub-gate portion, and
a volume of the first sub-gate portion is greater than a volume of the second sub-gate portion.
2. The semiconductor device of claim 1 , wherein a vertical height of the first sub-gate portion is greater than a vertical height of the second sub-gate portion.
3. The semiconductor device of claim 1 , wherein:
the plurality of insulating spacers include a first spacer disposed on a sidewall of the first sub-gate portion, and a second spacer disposed on a sidewall of the second sub-gate portion, and
a vertical height of the second spacer is greater than the vertical height of the second sub-gate portion.
4. The semiconductor device of claim 3 , wherein a vertical height of the first spacer is greater than the vertical height of the first sub-gate portion.
5. The semiconductor device of claim 3 , wherein a vertical height of the first spacer is less than the vertical height of the first sub-gate portion.
6. The semiconductor device of claim 3 , wherein a vertical height of the first spacer is greater than the vertical height of the second spacer.
7. A semiconductor device, comprising:
a substrate;
a fin protruding from the substrate;
a plurality of nanosheets disposed on the fin;
a gate disposed on the fin, the gate including a main gate portion on the plurality of nanosheets, and a plurality of sub-gate portions between the plurality of nanosheets and the fin;
a source/drain disposed on the fin, a central portion of the source/drain having a level lower than that of an outer portion thereof with respect to the substrate;
a plurality of insulating spacers disposed on sidewalls of the plurality of sub-gate portions; and
a plurality of air spaces directly contacting portions of the plurality of insulating spacers,
wherein:
each of the plurality of insulating spacers has at least one of a convex sidewall and a concave sidewall, and
the plurality of sub-gate portions include a first sub-gate portion and a second sub-gate portion, a volume of the first sub-gate portion being greater than a volume of the second sub-gate portion.
8. The semiconductor device of claim 7 , wherein a sidewall of each of the plurality of insulating spacers, which faces a corresponding sub-gate portion among the plurality of sub-gate portions, has a convex shape toward the corresponding sub-gate portion.
9. The semiconductor device of claim 7 , wherein a sidewall of each of the plurality of insulating spacers, which faces the source/drain, is concaved inward.
10. The semiconductor device of claim 7 , wherein outer sidewalls of the plurality of insulating spacers toward the source/drain are shifted inward from sidewalls of the plurality of nanosheets.
11. The semiconductor device of claim 7 , wherein the plurality of insulating spacers include a first spacer, and a second spacer disposed above the first spacer, and
a side surface of a sidewall of the first spacer is inclined with respect to the substrate, and a side surface of a sidewall of the second spacer is vertical with respect to the substrate.
12. The semiconductor device of claim 7 , wherein sidewalls of an insulating spacer, which is relatively closer to the substrate among the plurality of insulating spacers, are inclined with respect to the substrate.
13. The semiconductor device of claim 7 , wherein a vertical height of the first sub-gate portion being greater than a vertical height of the second sub-gate portion.
14. The semiconductor device of claim 13 , wherein:
the second sub-gate portion is disposed above the first sub-gate portion, and
the plurality of insulating spacers include a first spacer disposed on a sidewall of the first sub-gate portion, and a second spacer disposed on a sidewall of the second sub-gate portion.
15. The semiconductor device of claim 14 , wherein a lowermost surface of the first spacer is higher than a lowermost surface of the first sub-gate portion.
16. The semiconductor device of claim 7 , wherein the source/drain has a concave and convex surface in a direction of the plurality of nanosheets.
17. A semiconductor device, comprising:
a substrate;
a fin protruding from the substrate;
a plurality of nanosheets disposed on the fin;
a gate including molybdenum disposed on the fin, the gate including a plurality of sub-gate portions;
a source/drain disposed on the fin, a central portion of the source/drain having a level lower than that of an outer portion thereof with respect to the substrate; and
a plurality of insulating spacers disposed on sidewalls of the plurality of sub-gate portions,
wherein:
the gate includes a main gate portion on the plurality of nanosheets, and the plurality of sub-gate portions between the plurality of nanosheets and the fin,
the plurality of sub-gate portions include a first sub-gate portion, and a second sub-gate portion disposed above the first sub-gate portion, and
a volume of the first sub-gate portion is greater than a volume of the second sub-gate portion.
18. The semiconductor device of claim 17 , wherein the source/drain has a concave and convex surface in a direction of the plurality of nanosheets.
19. The semiconductor device of claim 17 , wherein each of the plurality of insulating spacers has at least one of a convex sidewall and a concave sidewall.
20. The semiconductor device of claim 17 , wherein a vertical height of the first sub-gate portion is greater than a vertical height of the second sub-gate portion.