IP Library › Granted Patent US 11,728,358
Granted Patent B2
US 11,728,358 · App. 17/476,591 · Granted Aug 15, 2023

Photoelectric conversion apparatus, image sensor, semiconductor apparatus, photoelectric conversion system, and equipment

Inventors: Mahito Shinohara (Tokyo, JP); Hiroshi Sekine (Kanagawa, JP)
Assignee: Canon Kabushiki Kaisha
H01L27/14616H01L27/1463H04N25/75H04N25/76
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Quick Facts
Patent No.
US 11,728,358
App. No.
17/476,591
Granted
Aug 15, 2023
Kind
B2
Abstract

A photoelectric conversion apparatus comprises a semiconductor layer including a first surface and a second surface, a first semiconductor region of a first conductivity type arranged in the semiconductor layer and configured to accumulate a signal charge generated by incident light, a second semiconductor region of the first conductivity type arranged in the semiconductor layer, a first transfer electrode configured to transfer the signal charge accumulated in the first semiconductor region to the second semiconductor region, a third semiconductor region of a second conductivity type arranged between the second semiconductor region and the second surface, and a fourth semiconductor region of the second conductivity type arranged between the third semiconductor region and the second surface. The third semiconductor region at least partially overlaps, in orthographic projection to the first surface, the second semiconductor region and the fourth semiconductor region.

Claims (44)

1. A photoelectric conversion apparatus comprising:

a semiconductor layer including a first surface and a second surface;

a first semiconductor region of a first conductivity type arranged in the semiconductor layer and configured to accumulate a signal charge generated by incident light;

a second semiconductor region of the first conductivity type arranged in the semiconductor layer;

a first transfer electrode arranged on the first surface and configured to form, in the semiconductor layer, a channel for transferring the signal charge accumulated in the first semiconductor region to the second semiconductor region;

a third semiconductor region of a second conductivity type arranged between the second semiconductor region and the second surface; and

a fourth semiconductor region of the second conductivity type arranged between the third semiconductor region and the second surface;

wherein the third semiconductor region at least partially overlaps the second semiconductor region in orthographic projection to the first surface,

the third semiconductor region at least partially overlaps the fourth semiconductor region in orthographic projection to the first surface, and

an effective value of an impurity concentration of an intermediate semiconductor region of the second conductivity type between the third semiconductor region and the fourth semiconductor region is not less than 2×10 13 cm −3 and not more than 1×10 15 cm −3 , and a width of the intermediate semiconductor region in a normal direction with respect to the first surface is not less than 0.13 μm and not more than 0.8 μm.

2. The apparatus according to claim 1 , wherein

a fifth semiconductor region of the second conductivity type is further arranged between the second semiconductor region and the fourth semiconductor region and in a position deeper than the third semiconductor region in the normal direction with respect to the first surface, and the fifth semiconductor region at least partially overlaps the second semiconductor region in orthographic projection to the first surface.

3. The apparatus according to claim 2 , wherein

the fourth semiconductor region and the fifth semiconductor region partially overlap each other in orthographic projection to the first surface.

4. The apparatus according to claim 2 , wherein

the third semiconductor region and the fifth semiconductor region partially overlap each other in orthographic projection to the first surface.

5. The apparatus according to claim 2 , wherein

a sixth semiconductor region of the second conductivity type is further arranged between the fourth semiconductor region and the second surface, and an effective value of an impurity concentration of a second intermediate semiconductor region between the fifth semiconductor region and the sixth semiconductor region is not less than 2×10 13 cm −3 and not more than 1×10 15 cm −3 , and a width of the second intermediate semiconductor region in a normal direction with respect to the first surface is not less than 0.13 μm and not more than 0.8 μm.

6. The apparatus according to claim 2 , wherein

an effective value of an impurity concentration of a third intermediate semiconductor region of the second conductivity type between the fourth semiconductor region and the fifth semiconductor region is not less than 2×10 13 cm −3 and not more than 1×10 15 cm −3 , and a width of the third intermediate semiconductor region in a normal direction with respect to the first surface is not less than 0.13 μm and not more than 0.8 μm.

7. The apparatus according to claim 1 , further comprising:

a floating diffusion region of the first conductivity type arranged between the first surface and the second surface; and

a second transfer electrode arranged on the first surface and configured to form, in the semiconductor layer, a channel for transferring the signal charge from the second semiconductor region to the floating diffusion region,

wherein a part of the second semiconductor region is arranged so as to overlap a part of the second transfer electrode in orthographic projection to the first surface.

8. The apparatus according to claim 7 , further comprising a transistor configured to amplify a signal from the floating diffusion region.

9. An image sensor comprising:

a pixel unit in which a pixel including a photoelectric conversion apparatus defined in claim 1 is arranged;

a vertical scanning circuit configured to control the pixel unit to read out a signal from the pixel; and

a processing circuit configured to process the signal read out from the pixel.

10. A semiconductor apparatus comprising:

a semiconductor device including a pixel unit in which a pixel including a photoelectric conversion apparatus defined in claim 1 is arranged; and

a package configured to store the semiconductor device.

11. A photoelectric conversion system comprising:

an optical system including a lens;

a pixel unit in which a pixel including a photoelectric conversion apparatus defined in claim 1 is arranged, the photoelectric conversion apparatus being configured to convert light having passed through the optical system into an electrical signal; and

a signal processing unit configured to process a signal output from the pixel unit.

12. An equipment that includes a photoelectric conversion apparatus defined in claim 1 ,

wherein the equipment further comprises at least one of

an optical apparatus corresponding to the photoelectric conversion apparatus;

a control apparatus configured to control the photoelectric conversion apparatus;

a processing apparatus configured to process a signal output from the photoelectric conversion apparatus;

a display apparatus configured to display information obtained by the photoelectric conversion apparatus;

a storage apparatus configured to store the information obtained by the photoelectric conversion apparatus; and

a mechanical apparatus configured to operate based on the information obtained by the photoelectric conversion apparatus.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2021
From: SHINOHARA, MAHITO; SEKINE, HIROSHI
To: CANON KABUSHIKI KAISHA
Reel/Frame 057697/0028 →
Priority Claims (1)
JP 2020-158968 · Sep 23, 2020 · national
Continuity (1)
Related Publication 20220093662A1 · Mar 24, 2022
Cited By (1)
US 12,701,811