2d-channel transistor structure with source-drain engineering

1. A method, comprising:

providing a workpiece having a semiconductor structure;

depositing a two-dimensional (2D) material layer over the semiconductor structure;

forming a dielectric feature inserted between the 2D material layer and the semiconductor structure;

forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and

forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature, wherein the gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor, and wherein the semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

2. The method of claim 1 , wherein

the semiconductor structure comprises silicon, germanium, a III-V semiconductor, or a II-VI semiconductor; and

the 2D material layer includes one of graphene, tungsten sulfide (WS 2 ), tungsten telluride (WTe 2 ), tungsten selenide (WSe 2 ), molybdenum sulfide (MoS 2 ), molybdenum telluride (MoTe 2 ), black phosphorus, and molybdenum selenide (MoSe 2 ).

3. The method of claim 1 , wherein the forming of the source feature and the drain feature includes

patterning the semiconductor structure to form trenches in source/drain regions; and

epitaxially growing a semiconductor material to fill in the trenches, thereby forming the source feature and the drain feature.

4. The method of claim 3 , wherein

the patterning of the semiconductor structure further includes patterning the 2D material layer; and

the epitaxially growing of the semiconductor material includes epitaxially growing the semiconductor material in direct contact with edges of the 2D material layer.

5. The method of claim 4 , wherein

the gate structure includes a gate stack and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and

the patterning of the 2D material layer includes patterning the 2D material layer such that the patterned 2D material layer spans between the first spacer and the second spacer of the gate spacer layer.

6. The method of claim 5 , wherein the patterning of the 2D material layer includes patterning the 2D material layer such that opposite edges of the patterned 2D material layer are aligned with outer sides of the first and second spacers, respectively.

7. The method of claim 3 , further comprising

forming a sacrificial semiconductor layer on the semiconductor structure before the depositing of the 2D material layer; and

replacing the sacrificial semiconductor layer with a dielectric layer through the trenches after the patterning of the semiconductor structure to form the trenches in source/drain regions.

8. The method of claim 1 , wherein the depositing of the 2D material layer includes

forming a dummy gate stack over the semiconductor structure and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the dummy gate stack;

removing the dummy gate stack after the forming of source feature and the drain feature, resulting a gate trench defined by the first and second spacers, the semiconductor structure is exposed within the gate trench; and

selectively depositing the 2D material layer on the semiconductor structure exposed within the gate trench such that the 2D material layer spans between inner sides of the first and second spacers, respectively.

9. The method of claim 8 , wherein the forming of the gate structure includes forming the gate structure on the 2D material layer within the gate trench.

10. The method of claim 1 , wherein the depositing of the 2D material layer includes depositing the 2D material layer with a thickness between about 2 Å and about 10 Å.

11. A method, comprising:

forming a semiconductor stack that includes first semiconductor layers and second semiconductor layers alternatively configured, wherein the first and second semiconductor layers are different in composition;

depositing a two-dimensional (2D) material layer on the second semiconductor layers;

forming a source feature and a drain feature electrically connected to the second semiconductor layers and the 2D material layer, wherein the source feature and drain feature include a semiconductor material;

selectively removing the first semiconductor layers; and

forming a gate structure over the two-dimensional material layer and extending to wrap around each of the second semiconductor layers.

12. The method of claim 11 , wherein

the second semiconductor layer includes one of silicon, germanium, a III-V semiconductor, and a II-VI semiconductor; and

the 2D material layer includes one of graphene, tungsten sulfide (WS 2 ), tungsten telluride (WTe 2 ), tungsten selenide (WSe 2 ), molybdenum sulfide (MoS 2 ), molybdenum telluride (MoTe 2 ), black phosphorus, and molybdenum selenide (MoSe 2 ).

13. The method of claim 11 , wherein the forming of the source feature and the drain feature includes

patterning the semiconductor structure to form trenches in source/drain regions; and

epitaxially growing a semiconductor material to fill in the trenches, thereby forming the source feature and the drain feature, wherein the second semiconductor layers span between the source feature and the drain feature.

14. The method of claim 13 , wherein the forming of the gate structure over the two-dimensional material layer and extending to wrap around each of the second semiconductor layers includes

forming a dummy gate structure over the semiconductor stack before the forming of the source feature and the drain feature;

removing the dummy gate structure after the forming of the source feature and the drain feature, resulting in a gate trench; and

forming a gate stack in the gate trench and spanned between the first and second gate spacers, wherein the selectively removing of the first semiconductor layers includes selectively removing the first semiconductor layers through the gate trench after the removing of the dummy gate structure.

15. The method of claim 14 , wherein the forming of the gate structure over the two-dimensional material layer and extending to wrap around each of the second semiconductor layers further includes

depositing a dielectric material layer in the gate trench after the removing of the dummy gate structure; and

performing an anisotropic etching process to the dielectric material layer before the forming of the gate stack, thereby forming a first gate spacer on a sidewall of the source feature and a second gate spacer on a sidewall of the drain feature.

16. The method of claim 15 ,

wherein the selectively removing of the first semiconductor layers includes selectively removing the first semiconductor layers through the gate trench after the removing of the dummy gate structure;

the depositing of the 2D material layer includes depositing the 2D material layer to wrap around the each of the second semiconductor layers; and

the depositing of the dielectric material layer in the gate trench includes depositing the dielectric material layer on the 2D material layer to wrap around the each of the second semiconductor layers.

17. The method of claim 15 , wherein the performing of the anisotropic etching process to the dielectric material layer includes performing the anisotropic etching process to the dielectric material layer, thereby forming inner spacers between adjacent two of the first semiconductor layers.

18. The method of claim 11 , wherein the depositing of the 2D material layer on the second semiconductor layers includes depositing the 2D material layer on a top surface and a bottom surface of the each of the second semiconductor layers.

19. A semiconductor device, comprising:

a channel member including a first channel layer and a second channel layer over the first channel layer;

a dielectric feature inserted between the 2D material layer and the semiconductor structure;

a gate structure over the channel member; and

a source feature and a drain feature of a semiconductor material,

wherein the first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor,

wherein the second channel layer includes a two-dimensional material,

wherein the two-dimensional material includes graphene, tungsten sulfide (WS 2 ), tungsten telluride (WTe 2 ), tungsten selenide (WSe 2 ), molybdenum sulfide (MoS 2 ), molybdenum telluride (MoTe 2 ), black phosphorus, or molybdenum selenide (MoSe 2 ), and

wherein the semiconductor material of the source and drain features electrically connects to the first and second channel layers.

20. The semiconductor device of claim 19 , wherein

the gate structure includes a gate stack and a gate spacer layer having a first spacer and a second spacer disposed on opposite sidewalls of the gate stack; and

the second channel layer spans between the first spacer and the second spacer of the gate spacer layer.