LSB dithering for segmented DACs

1. A digital to analog (DAC) circuit, comprising:

a main DAC;

an auxiliary code generator configured to produce an auxiliary code;

an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code;

first summing circuitry configured to sum an input digital code and the auxiliary code, and to provide the sum of the input digital code and the auxiliary code to the main DAC; and

second summing circuitry configured to subtract the analog version of the auxiliary code from an analog signal output from the main DAC,

wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

2. The DAC circuit of claim 1 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit.

3. The DAC circuit of claim 2 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate that is a sampling rate of the DAC circuit divided by N, where N is an integer greater than or equal to two.

4. The DAC circuit of claim 1 , wherein the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC.

5. The DAC circuit of claim 4 , wherein the auxiliary code has a smaller number of bits than the number of binary-weighted LSBs of the main DAC.

6. The DAC circuit of claim 5 , wherein the auxiliary DAC is configured to convert a smaller number of bits than the number of binary-weighted LSBs of the main DAC.

7. The DAC circuit of claim 1 , wherein the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

8. The DAC circuit of claim 7 , wherein the auxiliary code generator comprises a counter.

9. The DAC circuit of claim 1 , configured to perform two or more of:

i) the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit;

ii) the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC; and/or

iii) the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

10. The DAC circuit of claim 1 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

11. A digital to analog (DAC) circuit that performs least significant bit (LSB) dithering, the DAC circuit comprising:

a main DAC;

an auxiliary code generator configured to produce an auxiliary code;

an auxiliary DAC configured to receive the auxiliary code and convert the auxiliary code into an analog version of the auxiliary code; and

summing circuitry to dither LSBs of the main DAC with the auxiliary code,

wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and/or the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

12. The DAC circuit of claim 11 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit.

13. The DAC circuit of claim 12 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate that is a sampling rate of the DAC circuit divided by N, where N is an integer greater than or equal to two.

14. The DAC circuit of claim 11 , wherein the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC.

15. The DAC circuit of claim 14 , wherein the auxiliary code has a smaller number of bits than the number of binary-weighted LSBs of the main DAC.

16. The DAC circuit of claim 15 , wherein the auxiliary DAC is configured to convert a smaller number of bits than the number of binary-weighted LSBs of the main DAC.

17. The DAC circuit of claim 11 , wherein the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

18. The DAC circuit of claim 17 , wherein the auxiliary code generator comprises a counter.

19. The DAC circuit of claim 11 , configured to perform two or more of:

i) the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit;

ii) the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC; and/or

iii) the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.

20. The DAC circuit of claim 11 , wherein the auxiliary code generator is configured to update the auxiliary code at a rate less than a sampling rate of the DAC circuit, the auxiliary code has a smaller range than that of a range of binary-weighted LSBs of the main DAC and the auxiliary code generator is configured to produce the auxiliary code as a predetermined repeating sequence.