IP Library › Granted Patent US 11,728,962
Granted Patent B2
US 11,728,962 · App. 17/644,066 · Granted Aug 15, 2023

Multi-phase clock signal generation circuitry

Inventors: Shaojun Ma (San Jose, CA); Chi Fung Poon (Sunnyvale, CA); Kevin Zheng (San Jose, CA); Parag Upadhyaya (Los Gatos, CA)
Assignee: XILINX, INC.
H04L7/0037H03K19/21
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Quick Facts
Patent No.
US 11,728,962
App. No.
17/644,066
Granted
Aug 15, 2023
Kind
B2
Abstract

Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

Claims (67)

1. A clock generation circuitry comprising:

quadrature locked loop circuitry comprising first injection locked oscillator circuitry configured to:

receive a first input signal and a second input signal and output first clock signals, wherein the first input signal and the second input signal correspond to a reference clock signal; and

generate adjusted first clock signals based on a first control signal, wherein the first control signal is generated based on the first clock signals;

injection locked oscillator circuitry coupled to outputs of the first injection locked oscillator circuitry, and configured to receive the first control signal, receive the first clock signals, and generate second clock signals based on the first control signal; and

output circuitry configured to receive the second clock signals and generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, wherein frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than a frequency of the reference clock signal.

2. The clock generation circuitry of claim 1 , wherein the first injection locked oscillator circuitry and the second injection locked oscillator circuitry are configured to receive a first supply signal.

3. The clock generation circuitry of claim 1 , wherein the quadrature locked loop circuitry further comprises:

quadrature phase error detector circuitry configured to receive the first clock signals and output a first adjustment signal based on the first clock signals; and

voltage to current circuitry configured to receive the first adjustment signal and generate the first control signal based on the first adjustment signal, and wherein the first injection locked oscillator circuitry is further configured to receive the first control signal.

4. The clock generation circuitry of claim 3 , wherein the quadrature phase error detector circuitry is configured to generate the first adjustment signal based on a first phase error of a first pair of the first clock signals and a second phase error of a second pair of the first clock signals.

5. The clock generation circuitry of claim 1 , wherein the output circuitry comprises XOR circuitry, the XOR circuitry comprises:

a first NAND gate configured to receive a first one of the second clock signals and a second one of the second clock signals;

a second NAND gate configured to receive a third one of the second clock signals and a fourth one of the second clock signals;

a third NAND gate configured to receive the second one of the second clock signals and the third one of the second clock signals; and

a fourth NAND gate configured to receive the first one of the second clock signals and the fourth one of the second clock signals.

6. The clock generation circuitry of claim 5 , wherein the first NAND gate comprises:

a first transistor coupled between a first node, and an output node and comprising a gate configured to receive the second one of the second clock signals;

a second transistor coupled between the first node, and the output node and comprising a gate configured to receive the first one of the second clock signals;

a third transistor coupled to the output node, and comprising a gate configured to receive the second one of the second clock signals;

a fourth transistor coupled to the third transistor and a second node, and comprising a gate configured to receive the first one of the second clock signals;

a fifth transistor coupled to the output node, and comprising a gate configured to receive the first one of the second clock signals; and

a sixth transistor coupled to the fifth transistor and the second node, and comprising a gate configured to receive the second one of the second clock signals.

7. A communication system comprising:

transceiver circuitry configured to receive a reference clock signal, the transceiver circuitry comprising:

quadrature locked loop circuitry configured to generate differential input signals from the reference clock signal, the quadrature locked loop circuitry comprising a first injection locked oscillator circuitry configured to:

receive the differential input signals and output first clock signals; and

generate adjusted first clock signals based on a first control signal, wherein the first control signal is generated based on the first clock signals;

second injection locked oscillator circuitry coupled to outputs of the first injection locked oscillator circuitry and configured to receive the first control signal, receive the first clock signals, and generate second clock signals based on the first control signal; and

output circuitry configured to receive the second clock signals and generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, wherein frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than a frequency of the reference clock signal.

8. The communication system of claim 7 , wherein the first injection locked oscillator circuitry and the second injection locked oscillator circuitry are configured to receive a first supply signal.

9. The communication system of claim 7 , wherein the quadrature locked loop circuitry further comprises:

quadrature phase error detector circuitry configured to receive the first clock signals and output a first adjustment signal based on the first clock signals; and

voltage to current circuitry configured to receive the first adjustment signal and generate the first control signal based on the first adjustment signal, and wherein the first injection locked oscillator circuitry is further configured to receive the first control signal.

10. The communication system of claim 9 , wherein the quadrature phase error detector circuitry is configured to generate the first adjustment signal based on a first phase error of a first pair of the first clock signals and a second phase error of a second pair of the first clock signals.

11. The communication system of claim 7 , wherein the output circuitry is XOR circuitry, the XOR circuitry comprises:

a first NAND gate configured to receive a first one of the second clock signals and a second one of the second clock signals;

a second NAND gate configured to receive a third one of the second clock signals and a fourth one of the second clock signals;

a third NAND gate configured to receive the second one of the second clock signals and the third one of the second clock signals; and

a fourth NAND gate configured to receive the first one of the second clock signals and the fourth one of the second clock signals.

12. The communication system of claim 11 , wherein the first NAND gate comprises:

a first transistor coupled between a first node, and an output node and comprising a gate configured to receive the second one of the second clock signals;

a second transistor coupled between the first node, and the output node and comprising a gate configured to receive the first one of the second clock signals;

a third transistor coupled to the output node, and comprising a gate configured to receive the second one of the second clock signals;

a fourth transistor coupled to the third transistor and a second node, and comprising a gate configured to receive the first one of the second clock signals;

a fifth transistor coupled to the output node, and comprising a gate configured to receive the first one of the second clock signals; and

a sixth transistor coupled to the fifth transistor and the second node, and comprising a gate configured to receive the second one of the second clock signals.

13. A method comprising:

receiving a reference clock signal;

generating first and second differential signals from the reference clock signal;

generating, via first injection locked oscillator circuitry of quadrature locked loop circuitry, first clock signals from the first and second differential signals;

generating first adjusted clock signals based on a first control signal, wherein the first control signal is generated based on the first clock signals;

receiving, via second injection locked oscillator circuitry, the first control signal;

generating, via the second injection locked oscillator circuitry, second clock signals from the first clock signals based on the first control signal; and

generating, via output circuitry, a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal from the second clock signals, wherein frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than a frequency of the reference clock signal.

14. The method of claim 13 further comprising receiving, at the first injection locked oscillator circuitry and the second injection locked oscillator circuitry, a first supply signal.

15. The method of claim 13 further comprising:

generating, via quadrature phase error detector circuitry, a first adjustment signal based on the first clock signals, wherein the first control signal is generated based on the first adjustment signal; and

generating, via the first injection locked oscillator circuitry, the adjusted first clock signals based on the first control signal.

16. The method of claim 15 , wherein the first adjustment signal is generated based on a first phase error of a first pair of the first clock signals and a second phase error of a second pair of the first clock signals.

17. The method of claim 13 , wherein the output circuitry is XOR circuitry, the XOR circuitry comprises a first NAND gate configured to receive a first one of the second clock signals and a second one of the second clock signals, and wherein the first NAND gate comprises:

a first transistor coupled between a first node, and an output node and comprising a gate configured to receive the second one of the second clock signals;

a second transistor coupled between the first node, and the output node and comprising a gate configured to receive the first one of the second clock signals;

a third transistor coupled to the output node, and comprising a gate configured to receive the second one of the second clock signals;

a fourth transistor coupled to the third transistor and a second node, and comprising a gate configured to receive the first one of the second clock signals;

a fifth transistor coupled to the output node, and comprising a gate configured to receive the first one of the second clock signals; and

a sixth transistor coupled to the fifth transistor and the second node, and comprising a gate configured to receive the second one of the second clock signals.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2022
From: MA, SHAOJUN; POON, CHI FUNG; ZHENG, KEVIN; UPADHYAYA, PARAG
To: XILINX, INC.
Reel/Frame 059254/0955 →
Continuity (1)
Related Publication 20230188314A1 · Jun 15, 2023
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