IP Library › Granted Patent US 11,729,965
Granted Patent B2
US 11,729,965 · App. 17/849,854 · Granted Aug 15, 2023

Capacitor, semiconductor device, and manufacturing method of semiconductor device

Inventors: Yuichi Sato (Kanagawa, JP); Ryota Hodo (Kanagawa, JP); Yuta Iida (Kanagawa, JP); Tomoaki Moriwaka (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10B12/30H01L21/02266H01L21/02274H01L21/31116H01L21/3212H01L23/5329H10B12/02
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Quick Facts
Patent No.
US 11,729,965
App. No.
17/849,854
Granted
Aug 15, 2023
Kind
B2
Abstract

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor. The transistor includes a metal oxide and a first conductor that is electrically connected to the metal oxide. The capacitor includes a first insulator which is provided over the metal oxide and which the first conductor penetrates; a second insulator provided over the first insulator and including an opening reaching the first insulator and the first conductor; a second conductor in contact with an inner wall of the opening, the first insulator, and the first conductor; a third insulator provided over the second conductor; and a fourth conductor provided over the third insulator. The first insulator has higher capability of inhibiting the passage of hydrogen than the second insulator.

Claims (44)

1. A semiconductor device comprising:

a semiconductor layer;

a first insulator comprising a depressed portion over the semiconductor layer;

a first conductor electrically connected to the semiconductor layer, the first conductor penetrating the first insulator;

a second insulator over the first insulator, the second insulator comprising an opening overlapping with the depressed portion and the first conductor; and

a second conductor in direct contact with the depressed portion, a curved surface of the first conductor, and an inner wall of the opening,

wherein the first conductor penetrates the second insulator, and

wherein the first conductor comprises the curved surface in a portion above a top surface of the first insulator.

2. A semiconductor device comprising:

a semiconductor layer;

a first insulator comprising a depressed portion over the semiconductor layer;

a first conductor electrically connected to the semiconductor layer, the first conductor penetrating the first insulator;

a second insulator over the first insulator, the second insulator comprising an opening overlapping with the depressed portion and the first conductor;

a second conductor in direct contact with the depressed portion, a curved surface of the first conductor, and an inner wall of the opening;

a third insulator over the second conductor and in the opening; and

a third conductor over the third insulator,

wherein the third conductor overlaps with the semiconductor layer, and

wherein the first conductor comprises the curved surface in a portion above a top surface of the first insulator.

3. The semiconductor device according to claim 1 , wherein the first insulator comprises aluminum and oxygen.

4. The semiconductor device according to claim 1 ,

wherein the second insulator comprises:

a third insulator; and

a fourth insulator over the third insulator,

wherein one of the third insulator and the fourth insulator has compressive stress, and

wherein the other of the third insulator and the fourth insulator has tensile stress.

5. The semiconductor device according to claim 1 , wherein the semiconductor layer is an oxide semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the first insulator has higher capability of inhibiting passage of hydrogen than the second insulator.

7. The semiconductor device according to claim 1 ,

wherein a transistor comprises the semiconductor layer and the first conductor, and

wherein a capacitor comprises the second conductor.

8. The semiconductor device according to claim 2 , wherein the first insulator comprises aluminum and oxygen.

9. The semiconductor device according to claim 2 ,

wherein the second insulator comprises:

a fourth insulator; and

a fifth insulator over the fourth insulator,

wherein one of the fourth insulator and the fifth insulator has compressive stress, and

wherein the other of the fourth insulator and the fifth insulator has tensile stress.

10. The semiconductor device according to claim 2 , wherein the semiconductor layer is an oxide semiconductor layer.

11. The semiconductor device according to claim 2 , wherein the first insulator has higher capability of inhibiting passage of hydrogen than the second insulator.

12. The semiconductor device according to claim 2 ,

wherein a transistor comprises the semiconductor layer and the first conductor, and

wherein a capacitor comprises the second conductor, the third insulator, and the third conductor.

13. The semiconductor device according to claim 2 , wherein the third conductor and the second conductor face each other with the third insulator interposed therebetween, along the inner wall of the opening.

14. The semiconductor device according to claim 2 , wherein the third conductor and the second conductor face each other with the third insulator interposed therebetween, along the curved surface of the first conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2022
From: SATO, YUICHI; HODO, RYOTA; IIDA, YUTA; MORIWAKA, TOMOAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 060317/0551 →
Priority Claims (1)
JP 2017-013142 · Jan 27, 2017 · national
Continuity (2)
Continuation 16478532
Related Publication 20220359523A1 · Nov 10, 2022
Cited By (1)
US 12,453,187