Method and apparatus for generating metadata by a compiler

1. A system, comprising: a processor;

a compiler configured to

identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code;

compile the high-level function in the high-level code of an application into the set of low-level instructions to be executed on the hardware; and

generate a plurality of structured metadata associated with allocation of resources in the hardware to execute the set of low-level instructions.

2. The system of claim 1 , wherein the compiler comprises a plurality of backend compilers, and wherein a structured metadata from the plurality of structured metadata is selected and fed back into one backend compiler of the plurality of backend compilers, and wherein the selected structured metadata is used by the one backend compiler to optimize its operation.

3. The system of claim 1 , wherein the hardware is a machine learning (ML) hardware, and wherein the application is an ML operation.

4. The system of claim 1 , wherein the high-level code is associated with one or more of changing precision, quantization, dimension reordering, or splitting or copying data across one or more processing tiles of the hardware.

5. The system of claim 1 , wherein one or more processing operations to be performed associated with the high-level code reduces data movement.

6. The system of claim 1 , wherein the hardware is a dedicated hardware block including one or more microprocessors and/or on-chip memory (OCM) units storing the data and/or the set of low-level instructions compiled from the high-level function.

7. The system of claim 1 , wherein one or more processing operations to be performed associated with the high-level code reduces one or more of storage, computations, or data conversion.

8. The system of claim 1 , wherein the plurality of structured metadata is human readable.

9. The system of claim 1 , wherein the plurality of structured metadata is executable.

10. The system of claim 1 , wherein the plurality of structured metadata provides information associated with memory location storing data, and wherein the memory location storing the data is compared to expected data for verification or for debugging of the high-level function.

11. The system of claim 1 , wherein determining resources in the hardware includes mapping of operations and data to one or more tiles of the hardware to execute the set of low-level instructions.

12. The system of claim 1 , wherein the high-level function of the high-level code is optimized based on the plurality of structured metadata.

13. The system of claim 1 , wherein the compiler is further configured to:

receive a high-level function in a high-level code of the application;

divide the high-level function into core parts; and

check for lexical, grammar, and syntax.

14. A method, comprising:

receiving a high-level function in a high-level code of an application;

identifying resources in a hardware to execute a set of low-level instructions that is generated from the high-level function in the high-level code;

compiling the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware; and

generating a plurality of structured metadata associated with allocation of resources in the hardware to execute the set of low-level instructions.

15. The method of claim 14 further comprising:

selecting a structured metadata from the plurality of structured metadata;

feeding back the selected structured metadata into one backend compiler of the plurality of backend compilers; and

optimizing operation of the one backend compiler using the selected structured metadata.

16. The method of claim 14 , wherein the hardware is a machine learning (ML) hardware, and wherein the application is an ML operation.

17. The method of claim 14 , wherein one or more processing operations to be performed associated with the high-level code is one of changing precision, quantization, dimension reordering, or splitting or copying data across one or more processing tiles of the hardware.

18. The method of claim 14 , wherein the hardware is a dedicated hardware block including one or more microprocessors and/or on-chip memory (OCM) units storing the data and/or the set of low-level instructions compiled from the high-level function.

19. The method of claim 14 further comprising at least one of reducing storage or reducing computations or reducing data conversion or reducing data movement by using one or more processing operations to be performed associated with the high-level code.

20. The method of claim 14 , wherein the plurality of structured metadata is human readable.

21. The method of claim 14 , wherein the plurality of structured metadata is executable.

22. The method of claim 14 further comprising comparing data stored in a memory location as identified by a structured metadata of the plurality of structured metadata to expected data for verification of the high-level function.

23. The method of claim 14 further comprising:

comparing data stored in a memory location as identified by a structured metadata of the plurality of structured metadata to expected data; and

debugging of the high-level function based on the comparison.

24. The method of claim 14 further comprising determining resources in the hardware and mapping operations and data to one or more tiles of the hardware to execute the set of low-level instructions.

25. The method of claim 14 further comprising optimizing the high-level function of the high-level code based on the plurality of structured metadata.

26. A system, comprising: a processing means;

a means for receiving a high-level function in a high-level code of an application;

a means for identifying resources in a hardware to execute a set of low- level instructions that is generated from the high-level function in the high-level code;

a means for compiling the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware; and

a means for generating a plurality of structured metadata associated with allocation of resources in the hardware to execute the set of low-level instructions.