Method for fabricating semiconductor device with programmable anti-fuse feature
The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a peak portion on the substrate, forming a gate insulating layer on the substrate and the peak portion, forming a gate bottom conductive layer on the gate insulating layer, and forming a first doped region in the substrate and adjacent to one end of the gate insulating layer.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate;
forming a peak portion on the substrate;
forming a gate insulating layer on the substrate and the peak portion;
forming a gate bottom conductive layer on the gate insulating layer;
forming a first doped region in the substrate and adjacent to one end of the gate insulating layer; and
forming a plurality of first isolation structures in the substrate;
wherein the plurality of first isolation structures define a first active area, and the first doped region is formed in the first active area, wherein another end of the gate insulating layer is disposed on one of the plurality of first isolation structures.
2. The method for fabricating the semiconductor device of claim 1 , further comprising:
forming a gate top conductive layer on the gate bottom conductive layer.
3. The method for fabricating the semiconductor device of claim 2 , wherein forming the gate top conductive layer on the gate bottom conductive layer comprises:
forming a layer of a second conductive material over the gate bottom conductive layer, wherein the second conductive material comprises titanium, nickel, platinum, tantalum, or cobalt;
performing a thermal treatment on the semiconductor device; and
performing a clean process on the semiconductor device.
4. The method for fabricating the semiconductor device of claim 3 , wherein forming a peak portion on the substrate comprises an epitaxial growth process.