Semiconductor package
A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.
1. A semiconductor package, comprising:
a redistribution structure having an upper surface and a lower surface opposite to each other, and including:
a plurality of redistribution pads on the lower surface of the redistribution structure,
at least one redistribution pattern extending from one end of the plurality of redistribution pads and passing between at least one pair of redistribution pads among the plurality of redistribution pads,
a passivation layer having a first surface covering the plurality of redistribution pads and the at least one redistribution pattern, and a second surface opposite to the first surface, and
a plurality of dummy pads on the second surface of the passivation layer;
a semiconductor chip on the upper surface of the redistribution structure and electrically connected to the plurality of redistribution pads;
at least one connection bump on the plurality of redistribution pads; and
at least one dummy bump on the plurality of dummy pads,
wherein, on a plane parallel to the second surface, at least one dummy pad among the plurality of dummy pads is between the at least one pair of redistribution pads.
2. The semiconductor package as claimed in claim 1 , wherein the at least one redistribution pattern has a width narrower than a width of the plurality of redistribution pads.
3. The semiconductor package as claimed in claim 1 , wherein the passivation layer is in direct contact with the plurality of redistribution pads and the at least one redistribution pattern.
4. The semiconductor package as claimed in claim 1 , wherein the at least one dummy pad among the plurality of dummy pads is electrically insulated from the at least one redistribution pattern.
5. The semiconductor package as claimed in claim 1 , wherein:
the passivation layer has at least one opening extending from the first surface to the second surface, and
the at least one connection bump is electrically connected to at least one of the redistribution pads through the at least one opening of the passivation layer.
6. The semiconductor package as claimed in claim 1 , wherein the at least one dummy bump is spaced apart from the at least one redistribution pattern by the passivation layer.
7. The semiconductor package as claimed in claim 1 , wherein the at least one connection bump and the at least one dummy bump include the same material.
8. The semiconductor package as claimed in claim 1 , wherein the passivation layer includes a photo solder resist.
9. The semiconductor package as claimed in claim 1 , further comprising an encapsulant on the upper surface of the redistribution structure and encapsulating the semiconductor chip.
10. The semiconductor package as claimed in claim 1 , wherein, on a plane parallel to the second surface, at least one dummy pad among the plurality of dummy pads overlaps the at least one redistribution pattern.
11. A semiconductor package, comprising:
a redistribution structure having an upper surface and a lower surface opposite to each other, and including:
a plurality of redistribution pads on the lower surface of the redistribution structure,
at least one redistribution pattern extending from one end of the plurality of redistribution pads and passing between at least one pair of redistribution pads among the plurality of redistribution pads,
a passivation layer having a first surface covering the plurality of redistribution pads and the at least one redistribution pattern, and a second surface opposite to the first surface, and
a plurality of dummy pads on the second surface of the passivation layer;
a semiconductor chip on the upper surface of the redistribution structure and electrically connected to the plurality of redistribution pads;
at least one connection bump on the plurality of redistribution pads; and
at least one dummy bump on the plurality of dummy pads,
wherein, on a plane parallel to the second surface, at least one dummy pad among the plurality of dummy pads overlaps the at least one redistribution pattern in a direction perpendicular to the second surface.
12. The semiconductor package as claimed in claim 11 , wherein the at least one dummy pad does not overlap with the plurality of redistribution pads.
13. The semiconductor package as claimed in claim 11 , wherein the at least one pair of redistribution pads and the at least one redistribution pattern are on a same level.
14. The semiconductor package as claimed in claim 11 , wherein the at least one pair of redistribution pads and the at least one redistribution pattern are in direct contact with the first surface of the passivation layer.
15. The semiconductor package as claimed in claim 11 , wherein the plurality of dummy pads are in direct contact with the second surface of the passivation layer.
16. The semiconductor package as claimed in claim 11 , wherein the passivation layer is between the plurality of dummy pads and the at least one redistribution pattern.
17. The semiconductor package as claimed in claim 11 , wherein:
the redistribution structure further includes one or more insulating layers defining the upper surface and the lower surface, and
the plurality of redistribution pads are on a lowermost insulating layer among the one or more insulating layers.
18. The semiconductor package as claimed in claim 17 , wherein the one or more insulating layers and the passivation layer include different materials.
19. A semiconductor package, comprising:
a redistribution structure including an upper redistribution pad, a lower redistribution pad opposite to the upper redistribution pad, and a redistribution via electrically connecting the upper redistribution pad and the lower redistribution pad;
a semiconductor chip on the redistribution structure and electrically connected to the upper redistribution pad;
a passivation layer below the redistribution structure and covering the lower redistribution pad;
a connection bump penetrating through the passivation layer and electrically connected to the lower redistribution pad;
a dummy pad below the passivation layer and located on a level lower than the lower redistribution pad; and
a dummy bump below the dummy pad.
20. The semiconductor package as claimed in claim 19 , wherein:
the redistribution structure further includes at least one redistribution pattern extending from one end of the upper redistribution pad or the lower redistribution pad, and
the dummy pad is on a level lower than the at least one redistribution pattern.