Electrostatic discharge prevention
View Patent ↗The present disclosure provides embodiments of semiconductor structures. A semiconductor structure according to the present disclosure includes a substrate, a fin-shaped structure disposed over the substrate, the fin-shaped structure including a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers, a gate structure disposed over a channel region of the fin-shaped structure, a first source/drain feature extending through at least a first portion the fin-shaped structure, a second source/drain feature extending through at least a second portion of the fin-shaped structure, and a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.
1. A semiconductor device, comprising:
a substrate;
a fin-shaped structure disposed over the substrate, the fin-shaped structure comprising a plurality of first semiconductor layers interleaved by a plurality of second semiconductor layers;
a gate structure disposed over a channel region of the fin-shaped structure;
a first source/drain feature extending through at least a first portion the fin-shaped structure;
a second source/drain feature extending through at least a second portion of the fin-shaped structure; and
a backside metal line disposed below the substrate and spaced apart from the first source/drain feature and the second source/drain feature.
2. The semiconductor device of claim 1 ,
wherein the plurality of first semiconductor layers comprise silicon,
wherein the plurality of second semiconductor layers comprise silicon germanium.
3. The semiconductor device of claim 1 , wherein a thickness of the substrate is between about 20 nm and about 30 nm.
4. The semiconductor device of claim 1 ,
wherein the first source/drain feature comprises a first implantation region and the second source/drain feature comprises a second implantation region.
5. The semiconductor device of claim 4 , wherein the first implantation region comprises an n-type dopant.
6. The semiconductor device of claim 5 , wherein the second implantation region comprises a p-type dopant.
7. The semiconductor device of claim 1 , wherein the gate structure does not extend between adjacent ones of the plurality of first semiconductor layers.
8. The semiconductor device of claim 1 , wherein the gate structure is electrically floating.
9. The semiconductor device of claim 1 ,
wherein each of the first source/drain feature and the second source/drain feature extends through the fin-shaped structure and into the substrate.
10. A semiconductor structure, comprising:
a substrate comprising an electrostatic discharge (ESD) area, an n-type pick-up area, and a p-type pick-up area;
a first active region disposed over the n-type pick-up area;
a second active region disposed over the ESD area;
a third active region disposed over the p-type pick-up area;
an n-type implantation region over the n-type pick-up area and a first portion of the ESD area; and
a p-type implantation region over the p-type pick-up area and a second portion of the ESD area.
11. The semiconductor structure of claim 10 ,
wherein each of the n-type implantation region and the p-type implantation region is L-shaped in a top view.
12. The semiconductor structure of claim 10 ,
wherein the first active region comprises a first width,
wherein the second active region comprises a second width,
wherein a ratio of the second width to the first width is between 5 and 12.
13. The semiconductor structure of claim 10 , wherein the ESD area further comprises an intrinsic portion disposed between the first portion and the second portion.
14. The semiconductor structure of claim 13 , further comprising:
a first gate structure disposed over the first portion of the second active region;
a second gate structure disposed over the intrinsic portion of the second active region; and
a third gate structure disposed over the second portion of the second active region.
15. The semiconductor structure of claim 14 , further comprising:
a first backside power rail disposed below the substrate, wherein the first backside power rail is disposed directly below the first active region, and
a second backside power rail disposed below the substrate, wherein the second backside power rail is disposed directly below the first gate structure.
16. The semiconductor structure of claim 15 , wherein the second backside power rail is spaced apart from the intrinsic portion by at least 100 nm.
17. The semiconductor structure of claim 15 , wherein the second backside power rail is completely within a vertical projection area of the n-type implantation region.
18. A semiconductor structure, comprising:
a substrate comprising an electrostatic discharge (ESD) area, an n-type pick-up area, and a p-type pick-up area;
a first active region disposed over the n-type pick-up area;
a second active region disposed over the ESD area;
a third active region disposed over the p-type pick-up area;
an n-type implantation region over the n-type pick-up area and a first portion of the ESD area;
a p-type implantation region over the p-type pick-up area and a second portion of the ESD area;
a first gate structure disposed over the first portion of the second active region;
a second gate structure disposed over an intrinsic portion of the second active region, the intrinsic portion being disposed between the first portion and the second portion; and
a third gate structure disposed over the second portion of the second active region.
19. The semiconductor structure of claim 18 , wherein each of the first gate structure, the second gate structure and the third gate structure is electrically floating.
20. The semiconductor structure of claim 18 , wherein each of the first active region, the second active region and the third active region comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers.