Stacked semiconductor device having mirror-symmetric pattern
A stacked semiconductor device includes: a substrate; a 1 st transistor formed on a substrate, and including a 1 st active region surrounded by a 1 st gate structure and 1 st source/drain regions; and a 2 nd transistor stacked on the 1 st transistor, and including a 2 nd active region surrounded by a 2 nd gate structure and 2 nd source/drain regions, wherein the 1 st active region and the 1 st gate structure are vertically mirror-symmetric to the 2 nd active region and the 2 nd gate structure, respectively, with respect to a virtual plane therebetween.
1. A stacked semiconductor device comprising:
a substrate;
a 1 st transistor formed on a substrate, and comprising a 1 st active region surrounded by a 1 st gate structure, and 1 st source/drain regions connected by the 1 st active region, the 1 st source/drain regions being horizontally opposite to each other with respect to the 1 st active region;
a 2 nd transistor stacked on the 1 st transistor, and comprising a 2 nd active region surrounded by a 2 nd gate structure, and 2 nd source/drain regions connected by the 2 nd active region, the 2 nd source/drain regions being horizontally opposite to each other with respect to the 2 nd active region;
a 1 st isolation layer interposed between the 1 st active region and the 2 nd active region; and
a 2 nd isolation layer interposed between the 1 st gate structure and the 2 nd gate structure,
wherein the 2 nd isolation layer vertically overlaps only the 1 st and 2 nd gate structures among the 1 st and 2 nd active regions and the 1 st and 2 nd gate structures, wherein the 1 st active region and the 1 st gate structure are vertically mirror-symmetric to the 2 nd active region and the 2 nd gate structure, respectively, with respect to a virtual plane therebetween, and
wherein a gate dielectric layer is formed on the 2 nd isolation layer.
2. The stacked semiconductor device of claim 1 , wherein no middle-of-the-line (MOL) contact structure is formed between the 1 st transistor and the 2 nd transistor.
3. The stacked semiconductor device of claim 2 , further comprising an interconnect structure formed at a side of a stack of the 1 st transistor and the 2 nd transistor,
wherein the interconnect structure comprises a backend-of-the-line (BEOL) structure, and
wherein at least one of the 1 st source/drain regions and at least one of the 2 nd source/drain regions are connected to each other through the interconnect structure.
4. The stacked semiconductor device of claim 3 , wherein the BEOL structure includes a through-silicon via (TSV).
5. The stacked semiconductor device of claim 2 , wherein the 1 st gate structure and the 2 nd gate structure comprises a same work function material.
6. The stacked semiconductor device of claim 2 , wherein the 1 st gate structure and the 2 nd gate structure comprises different work function materials.
7. The stacked semiconductor device of claim 2 , wherein the 1 st transistor and the 2 nd transistor both comprise a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS).
8. The stacked semiconductor device of claim 2 , wherein the 1 st transistor and the 2 nd transistor comprise a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS), respectively, or an NMOS and a PMOS, respectively.
9. The stacked semiconductor device of claim 2 , wherein each of the 1 st transistor and the 2 nd transistor is a nanosheet transistor or a fin field-effect transistor.
10. A stacked semiconductor device comprising:
a substrate;
a 1 st transistor formed on a substrate, and comprising a 1 st active region surrounded by a 1 st gate structure, and 1 st source/drain regions connected by the 1 st active region;
a 2 nd transistor stacked on the 1 st transistor, and comprising a 2 nd active region surrounded by a 2 nd gate structure, and 2 nd source/drain regions connected by the 2 nd active region;
a 1 st isolation layer interposed between the 1 st active region and the 2 nd active region;
a 2 nd isolation layer interposed between the 1 st gate structure and the 2 nd gate structure; and
an interlayer dielectric (ILD) layer at a side of each of the 1 st gate structure and the 2 nd gate structure,
wherein the 1 st active region and the 1 st gate structure are vertically mirror-symmetric to the 2 nd active region and the 2 nd gate structure, respectively, with respect to a virtual plane therebetween,
wherein a gate dielectric layer is formed on the 2 nd isolation layer, and
wherein the gate dielectric layer is formed between the ILD layer and each of the 1 st gate structure and the 2 nd gate structure.
11. A stacked semiconductor device comprising:
a substrate;
a 1 st transistor formed on a substrate, and comprising a 1 st active region surrounded by a 1 st gate structure, and 1 st source/drain regions connected by the 1 st active region;
a 2 nd transistor stacked on the 1 st transistor, and comprising a 2 nd active region surrounded by a 2 nd gate structure, and 2 nd source/drain regions connected by the 2 nd active region;
a 1 st isolation layer interposed between the 1 st active region and the 2 nd active region;
a 2 nd isolation layer interposed between the 1 st gate structure and the 2 nd gate structure; and
an interlayer dielectric (ILD) layer at a side of the 1 st gate structure and the 2 nd gate structure,
wherein the 1 st active region and the 1 st gate structure are vertically mirror-symmetric to the 2 nd active region and the 2 nd gate structure, respectively, with respect to a virtual plane therebetween, and
wherein a gate dielectric layer is formed between the ILD layer and each of the 1 st gate structure and the 2 nd gate structure.
12. The stacked semiconductor device of claim 11 , wherein the ILD layer is formed at a side surface of the 2 nd isolation layer with the gate dielectric layer therebetween.
13. The stacked semiconductor device of claim 11 , wherein the 1 st transistor and the 2 nd transistor both comprise a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS).
14. The stacked semiconductor device of claim 11 , wherein the 1 st transistor and the 2 nd transistor comprise a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS), respectively, or an NMOS and a PMOS, respectively.
15. The stacked semiconductor device of claim 11 , wherein each of the 1 st transistor and the 2 nd transistor is a nanosheet transistor or a fin field-effect transistor.
16. The stacked semiconductor device of claim 11 , further comprising:
a 1 st metal pattern connected to the 1 st gate structure; and
a 2 nd metal pattern connected to the 2 nd gate structure and vertically mirror-symmetrical to the 1 st metal pattern with respect to the virtual plane.