Semiconductor devices with dielectric fins and method for forming the same

1. A method, comprising:

providing a structure having two fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over each of the fins; a dielectric fin oriented lengthwise parallel to the fins and disposed between the two fins and over the isolation structure; a dummy gate stack over the isolation structure, the fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack, wherein the dielectric fin comprises a portion disposed directly under the dummy gate stack;

removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the portion of the dielectric fin is exposed in the gate trench;

after the removing of the dummy gate stack, trimming the portion of the dielectric fin to reduce a width of the portion of the dielectric fin;

after the trimming, forming a high-k metal gate in the gate trench.

2. The method of claim 1 , further comprising:

etching back the high-k metal gate to a level below a top surface of the dielectric fin, thereby separating the high-k metal gate into two segments disposed on two sides of the dielectric fin; and

depositing a dielectric cap over the two segments of the high-k metal gate and the dielectric fin.

3. The method of claim 2 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer over the low-k dielectric layer, wherein a top surface of the two segments of the high-k metal gate is above a top surface of the low-k dielectric layer and below a top surface of the high-k dielectric layer.

4. The method of claim 1 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming of the dielectric fin includes completely removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer.

5. The method of claim 4 , wherein the trimming of the dielectric fin further includes etching the low-k dielectric layer after the completely removing of the high-k dielectric layer from the sidewalls of the low-k dielectric layer.

6. The method of claim 1 , wherein the trimming of the portion of the dielectric fin reduces a width of the portion of the dielectric fin by about 2 nm to about 12 nm.

7. The method of claim 1 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming of the dielectric fin includes partially removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer and keeping at least a portion of the high-k dielectric layer disposed on the sidewalls of the low-k dielectric layer.

8. The method of claim 1 , wherein the dielectric fin includes one or more high-k dielectric layers that extend a full width of the dielectric fin.

9. The method of claim 1 , wherein the dielectric fin is a first dielectric fin and the structure further includes a second dielectric fin adjacent one of the fins, before the removing of the dummy gate stack, further comprising:

partially recessing the dummy gate stack to a level below a top surface of the first and the second dielectric fins;

forming an etch mask covering the first dielectric fin and exposing the second dielectric fin;

recessing the second dielectric fin; and

removing the etch mask.

10. A method, comprising:

providing a structure having fins extending from a substrate; an isolation structure isolating bottom portions of the fins; source/drain (S/D) features over the fins; dielectric fins oriented lengthwise parallel to the fins, disposed between two adjacent fins of the fins and over the isolation structure, and isolating the S/D features; a dummy gate stack over the isolation structure, the fins, and the dielectric fins; and one or more dielectric layers over sidewalls of the dummy gate stack;

partially recessing the dummy gate stack, thereby exposing portions of the dielectric fins;

forming an etch mask covering a first dielectric fin of the dielectric fins and exposing a second dielectric fin of the dielectric fins;

partially etching the second dielectric fin through the etch mask, such that a top surface of the second dielectric fin is below a top surface of the first dielectric fin;

removing the etch mask;

removing the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein at least the first dielectric fin is exposed in the gate trench;

trimming the first dielectric fin to reduce a width of the first dielectric fin; and

after the trimming, forming a high-k metal gate in the gate trench.

11. The method of claim 10 , further comprising:

etching back the high-k metal gate to a level below the top surface of the first dielectric fin and above the top surface of the second dielectric fin, thereby separating the high-k metal gate into two segments disposed on two sides of the first dielectric fin; and

depositing a dielectric cap over the two segments of the high-k metal gate and the first dielectric fin.

12. The method of claim 10 , wherein each of the first and the second dielectric fins includes a low-k dielectric layer and a high-k dielectric layer over the low-k dielectric layer, wherein the partially etching of the second dielectric fin completely removes the high-k dielectric layer of the second dielectric fin.

13. The method of claim 10 , wherein each of the first and the second dielectric fins includes a low-k dielectric layer and a high-k dielectric layer over the low-k dielectric layer, wherein the partially etching of the second dielectric fin partially removes the high-k dielectric layer of the second dielectric fin.

14. The method of claim 10 , wherein the trimming of the first dielectric fin also reduces a width of the second dielectric fin.

15. The method of claim 10 , wherein the first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming of the first dielectric fin includes completely removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer.

16. The method of claim 10 , wherein the first dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming of the first dielectric fin includes partially removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer and keeping at least a portion of the high-k dielectric layer disposed on the sidewalls of the low-k dielectric layer.

17. A method, comprising:

providing a structure having two semiconductor fins extending from a substrate; an isolation structure isolating bottom portions of the semiconductor fins from each other; a dielectric fin oriented lengthwise parallel to the semiconductor fins and disposed between the two semiconductor fins and over the isolation structure; a dummy gate stack over the isolation structure, the semiconductor fins, and the dielectric fin; and one or more dielectric layers over sidewalls of the dummy gate stack;

etching the dummy gate stack to result in a gate trench within the one or more dielectric layers, wherein the dielectric fin is exposed in the gate trench;

trimming a width of the dielectric fin;

after the trimming, forming a high-k metal gate in the gate trench; and

etching back the high-k metal gate to a level below a top surface of the dielectric fin, thereby separating the high-k metal gate into two segments disposed on two sides of the dielectric fin.

18. The method of claim 17 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer over the low-k dielectric layer, wherein a top surface of the two segments of the high-k metal gate is above a top surface of the low-k dielectric layer and below a top surface of the high-k dielectric layer.

19. The method of claim 17 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming includes partially removing the high-k dielectric layer from the sidewalls of the low-k dielectric layer.

20. The method of claim 17 , wherein the dielectric fin includes a low-k dielectric layer and a high-k dielectric layer disposed on sidewalls of the low-k dielectric layer, wherein the trimming includes etching both the high-k dielectric layer and the low-k dielectric layer.