Semiconductor devices and methods of manufacturing the same

1. A method of manufacturing a semiconductor device, the method comprising:

forming a fin structure on a substrate, the fin structure comprising sacrificial lines and semiconductor lines that are alternately and repeatedly stacked;

forming a dummy gate structure on the fin structure and the substrate, the dummy gate structure comprising a dummy gate insulation pattern and a dummy gate electrode that are sequentially stacked;

etching the fin structure using the dummy gate structure as an etching mask to expose an upper surface of the substrate;

etching sidewalls of the sacrificial lines to form a first recess;

etching a portion of the dummy gate insulation pattern exposed by the first recess to form a second recess;

forming a first spacer in the first and second recesses;

forming a source/drain layer on the upper surface of the substrate; and

replacing the dummy gate structure with a gate structure.

2. The method of claim 1 , wherein the fin structure extends in a first direction substantially parallel to the upper surface of the substrate, and the dummy gate structure extends in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction.

3. The method of claim 2 , wherein forming the dummy gate structure comprises:

conformally forming a dummy gate insulation layer on the fin structure and the substrate;

forming a dummy gate electrode layer on the dummy gate insulation layer; and

patterning the dummy gate electrode layer and the dummy gate insulation layer using an etching mask extending in the second direction to form the dummy gate electrode and the dummy gate insulation pattern, respectively.

4. The method of claim 3 , wherein a protrusion portion of the dummy gate insulation pattern comprises a slanted sidewall that is not overlapped by the dummy gate electrode in a vertical direction substantially perpendicular to the upper surface of the substrate.

5. The method of claim 4 , wherein forming the second recess comprises removing the protrusion portion of the dummy gate insulation pattern.

6. The method of claim 2 , further comprising, after forming the dummy gate structure, forming a second spacer on the dummy gate structure,

wherein etching the fin structure is performed using the dummy gate structure and the second spacer as an etching mask.

7. The method of claim 6 , wherein the first and second spacers at least partially overlap with each other in a vertical direction substantially perpendicular to the upper surface of the substrate.

8. The method of claim 6 , wherein replacing the dummy gate structure with the gate structure comprises:

forming an insulation layer on the source/drain layer and on an outer sidewall of the second spacer;

removing the dummy gate structure to form an opening; and

forming the gate structure in the opening.

9. The method of claim 8 ,

wherein forming the source/drain layer comprises performing a selective epitaxial growth (SEG) process on the upper surface of the substrate, and

wherein the source/drain layer contacts an outer sidewall of the first spacer.

10. The method of claim 9 , wherein the opening does not expose the source/drain layer.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a fin structure on a substrate, the fin structure extending in a first direction;

forming a dummy gate structure on the fin structure and the substrate, the dummy gate structure comprising a dummy gate insulation pattern and a dummy gate electrode sequentially stacked and extending in a second direction substantially perpendicular to the first direction, wherein a protrusion portion of the dummy gate insulation pattern does not overlap the dummy gate electrode in a vertical third direction substantially perpendicular to an upper surface of the substrate;

forming a second spacer on a sidewall of the dummy gate structure;

etching the fin structure using the dummy gate structure and the second spacer as an etching mask to expose the upper surface of the substrate;

etching a portion of the fin structure to form a first recess;

etching the protrusion portion of the dummy gate insulation pattern to form a second recess;

forming a first spacer in the first and second recesses;

forming a source/drain layer on the upper surface of the substrate; and

replacing the dummy gate structure with a gate structure;

wherein forming the dummy gate structure comprises:

conformally forming a dummy gate insulation layer on the fin structure and the substrate;

forming a dummy gate electrode layer on the dummy gate insulation layer; and

patterning the dummy gate electrode layer and the dummy gate insulation layer using an etching mask extending in the second direction to form the dummy gate electrode and the dummy gate insulation pattern, respectively.

12. The method of claim 11 , wherein the protrusion portion of the dummy gate insulation pattern comprises a slanted sidewall.

13. The method of claim 11 ,

wherein the fin structure comprises sacrificial lines and semiconductor lines that are alternately and repeatedly stacked on the substrate, and

wherein forming the first recess comprises etching sidewalls of the sacrificial lines.

14. The method of claim 11 , wherein replacing the dummy gate structure with the gate structure comprises:

forming an insulation layer on the source/drain layer and on an outer sidewall of the second spacer;

removing the dummy gate structure to form an opening; and

forming the gate structure in the opening.

15. A method of manufacturing a semiconductor device, the method comprising:

forming a fin structure on a substrate, the fin structure extending in a first direction;

forming a dummy gate structure on the fin structure and the substrate, the dummy gate structure comprising a dummy gate insulation pattern and a dummy gate electrode sequentially stacked and extending in a second direction substantially perpendicular to the first direction, wherein a protrusion portion of the dummy gate insulation pattern does not overlap the dummy gate electrode in a third direction substantially perpendicular to an upper surface of the substrate;

forming a second spacer on a sidewall of the dummy gate structure, the second spacer covering at least a sidewall of the protrusion portion of the dummy gate insulation pattern;

etching the fin structure using the dummy gate structure and the second spacer as an etching mask to expose the upper surface of the substrate;

etching a portion of the fin structure to form a first recess;

etching the protrusion portion of the dummy gate insulation pattern to form a second recess;

forming a first spacer in the first and second recesses;

forming a source/drain layer on the upper surface of the substrate; and

replacing the dummy gate structure with a gate structure.

16. The method of claim 15 , wherein the first spacer comprises a central portion, overlapping at least a portion of the fin structure in the third direction, and a protrusion portion protruding from the central portion in the second direction, and wherein the central portion and the protrusion portion of the first spacer are formed of different materials.