Microelectronic assemblies having conductive structures with different thicknesses
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.
1. A microelectronic assembly, comprising:
a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) doped by an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum;
a first conductive trace having a first thickness in the PID, wherein the first thickness is between 4 um and 143 um; and
a second conductive trace having a second thickness in the PID, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first and second conductive traces have sloped sidewalls.
2. The microelectronic assembly of claim 1 , wherein the electroless catalyst in the PID has a weight percent of up to 10.
3. The microelectronic assembly of claim 1 , wherein the electroless catalyst in the PID is palladium having a weight percent of up to 5.
4. The microelectronic assembly of claim 1 , wherein the substrate layer is in an interposer.
5. A microelectronic assembly, comprising:
a first conductive feature having a first thickness in an electroless catalyst-doped photo-imageable dielectric (PID) layer of a substrate, wherein the first thickness is between 4 um and 143 um; and
a second conductive feature having a second thickness in the PID layer of the substrate, wherein the second thickness is between 2 um and 141 um, wherein the second thickness is different from the first thickness, and wherein the first and second conductive features have sloped sidewalls.
6. The microelectronic assembly of claim 5 , wherein the PID includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum.
7. The microelectronic assembly of claim 5 , wherein the first and second conductive features are traces.
8. The microelectronic assembly of claim 5 , further comprising:
a die electrically coupled to the substrate.
9. The microelectronic assembly of claim 8 , wherein the die is a central processing unit, a radio frequency chip, a power converter, or a network processor.
10. A computing device, comprising:
a package substrate having a first surface and an opposing second surface, the package substrate comprising:
a layer including an electroless catalyst-doped photo-imageable dielectric (PID);
a first conductive trace having a first thickness in the PID wherein the first thickness is between 4 um and 143 um; and
a second conductive trace having a second thickness in the PID wherein the second thickness is between 2 um and 141 um, wherein the second thickness is different from the first thickness, and wherein the first and second conductive traces have sloped sidewalls;
a circuit board coupled to the first surface of the package substrate; and
a die coupled to the second surface of the package substrate.
11. The computing device of claim 10 , wherein the PID includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, or tantalum.
12. The computing device of claim 10 , wherein the computing device is a server device.
13. The computing device of claim 10 , wherein the computing device is a portable computing device.