Semiconductor device and manufacturing method thereof
The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X 1 and a width X 2 . The width X 1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X 2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X 1 is greater than or equal to X 2.
1. A semiconductor device, comprising:
a substrate;
at least one bit line disposed on the substrate, wherein a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion;
at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug comprises at least one conductive layer, when viewed from a cross-sectional view, the storage node contact plug defines a width X 1 and a width X 2 , wherein the width X 1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X 2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, and wherein the width X 1 is greater than or equal to the width X 2 ; and
at least one dielectric layer covering a portion of the rounding hard mask and directly contacting the rounding hard mask.
2. The semiconductor device of claim 1 , wherein the top portion of the rounding hard mask is not a flat surface.
3. The semiconductor device of claim 1 , when viewed from the cross-sectional view, the rounding hard mask comprises a top surface and a bottom surface, the height of the rounding hard mask is defined as H, and the width of the bottom surface of the rounding hard mask is defined as W 1 , the width at a height ¼ H from the top surface of the rounding hard mask is defined as W 2 , wherein W 2 /W 1 <0.5.
4. The semiconductor device of claim 1 , when viewed from the cross-sectional view, the rounding hard mask comprises a top surface and a bottom surface, the height of the rounding hard mask is defined as H, and the width of the bottom surface of the rounding hard mask is defined as W 1 , the width at a height ½ H from the top surface of the rounding hard mask is defined as W 3 , wherein W 3 /W 1 <0.7.
5. The semiconductor device of claim 1 , wherein the storage node contact plug further comprises a polysilicon layer disposed under the conductive layer.
6. The semiconductor device of claim 5 , further comprising a silicide layer disposed between the conductive layer and the polysilicon layer.
7. The semiconductor device of claim 5 , further comprising a storage node pad disposed under the polysilicon layer, wherein the storage node pad is electrically connected to a first diffusion region in the substrate.
8. The semiconductor device of claim 1 , further comprising at least one spacer disposed between the storage node contact plug and the bit line.
9. The semiconductor device of claim 1 , further comprising a bit line storage node contact structure disposed under the bit line and directly contacting the bit line, wherein the bit line storage node contact structure is electrically connected to a second diffusion region in the substrate.