High density ReRAM integration with interconnect

1. An apparatus comprising:

a substrate;

a plurality of first columns parallel to each other and extending up from a top surface of the substrate, wherein each of the plurality of first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers;

a plurality of second columns extending parallel to each other and extending perpendicular to the plurality of first columns, wherein the plurality of second columns are located on top of the plurality of first columns such that the plurality of second columns crosses over the plurality of first columns, wherein each of the plurality of second columns includes at least one downwards extending protrusion, wherein the at least one downwards extending protrusion is in contact with one of the plurality of first columns; and

a dielectric layer located in a space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

2. The apparatus of claim 1 , wherein the plurality of layers of each ReRAM stack is comprised of:

a first layer comprised of first material;

a second layer formed on the first layer, wherein the second layer is comprised of a second material that is different than the first material;

a third layer formed on the second layer, wherein the third layer is comprised of a third material that is different than the first material and the second material;

a fourth layer formed o the third layer, wherein the fourth layer is comprised of the second material; and

a fifth layer formed on the fourth layer, wherein the fourth layer is comprised of the first material.

3. The apparatus of claim 2 , wherein the first material is TaN, wherein the second material is TiN, and wherein the third material is HfO2.

4. The apparatus of claim 2 , wherein the dielectric layer is in direct contact with sidewalls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

5. The apparatus of claim 1 , wherein each of a first columns are comprised of:

a first liner formed on the substrate;

a first metal layer formed on the liner; and

the ReRAM stack formed on the first metal layer.

6. The apparatus of claim 5 , wherein the ReRAM stack is in direct contact with one of the pluralities of second columns.

7. The apparatus of claim 6 , wherein each of the second columns is comprised of:

a second liner formed directly on the dielectric layer and on top of the ReRAM stack; and

a second metal layer formed directly on the second liner.

8. The apparatus of claim 6 , wherein the dielectric layer extends higher than each of the first columns, creating a channel between a side wall of the dielectric layer and the top of the ReRAM stack.

9. The apparatus of claim 8 , wherein each of the second columns is comprised of:

a second liner formed directly on the dielectric layer and the top of the ReRAM stack, such that the second liner is formed on the walls of the channel; and

a second metal layer formed directly on the second liner, such that, the second metal layer fills the channel to form the downward extending protrusion.

10. A microelectronic device comprising:

a logic array and a ReRAM array located on a substrate;

the ReRAM array is comprised of:

a plurality of first columns parallel to each other and extending up from a top surface of the substrate, wherein each of the plurality of first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers;

a plurality of second columns extending parallel to each other and extending perpendicular to the plurality of first columns, wherein the plurality of second columns are located on top of the plurality of first columns such that the plurality of second columns crosses over the plurality of first columns; and

a first dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the first dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack;

the Logic array is comprised of:

a plurality of third columns parallel to each other and extending up from a top surface of the substrate;

a plurality of fourth columns extending parallel to each other and extending perpendicular to the plurality of third columns, wherein the plurality of fourth columns are located on top of the plurality of third columns such that the plurality of fourth columns crosses over the plurality of third columns, wherein the plurality of fourth columns include downwards extensions, wherein the downward extension forms a connection with one of the plurality of third columns;

a second dielectric layer filling in the space between the plurality of third columns and the plurality of fourth columns.

11. The microelectronic device of claim 10 , wherein the plurality of layers of each ReRAM stack is comprised of:

a first layer comprised of first material;

a second layer formed on the first layer, wherein the second layer is comprised of a second material that is different than the first material;

a third layer formed on the second layer, wherein the third layer is comprised of a third material that is different than the first material and the second material;

a fourth layer formed on the third layer, wherein the fourth layer is comprised of the second material; and

a fifth layer formed on the fourth layer, wherein the fourth layer is comprised of the first material.

12. The microelectronic device of claim 11 , wherein the first material is TaN, wherein the second material is TiN, and wherein the third material is HfO2.

13. The microelectronic device of claim 11 , wherein the first dielectric layer is in direct contact with the sidewalls of the first layer, the second layer, the third layer, the fourth layer, and the fifth layer.

14. The microelectronic device of claim 10 , wherein each of a first columns are comprised of:

a first liner formed on the substrate;

a first metal layer formed on the liner; and

the ReRAM stack formed on the first metal layer.

15. The microelectronic device of claim 14 , wherein the ReRAM stack is in direct contact with one of the pluralities of second columns.

16. The microelectronic device of claim 15 , wherein each of the second columns is comprised of:

a second liner formed directly on the first dielectric layer and the top of the ReRAM stack; and

a second metal layer formed directly on the second liner.

17. The microelectronic device of claim 15 , wherein the first dielectric layer extends higher than each of the first columns, creating a channel between a side wall of the first dielectric layer and the top of the ReRAM stack.

18. The microelectronic device of claim 17 , wherein each of the second columns is comprised of:

a second liner formed directly on the first dielectric layer and the top of the ReRAM stack, such that the second liner is formed on the walls of the channel; and

a second metal layer formed directly on the second liner, such that, the second metal layer fills the channel.

19. The microelectronic device of claim 11 , wherein a portion of the second dielectric layer is located directly above a portion of one of the plurality of third columns, wherein the portion of the second dielectric layer is in direct contact with a sidewall of one of the plurality of columns.