In-memory associative processing system

1. An apparatus, comprising:

a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and

logic coupled with the memory die and configured to:

receive signaling that indicates a set of instructions from a host device, the set of instructions indicating a first vector and a second vector as operands for a computational operation;

select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing; and

write data representative of the first vector and the second vector to a set of planes of one or more tiles based at least in part on the selected vector mapping scheme.

2. The apparatus of claim 1 , wherein the logic is further configured to:

perform, using associative processing, the computational operation on the data representative of the first vector and the second vector; and

write data representative of a third vector that is a result of the computational operation to the set of planes.

3. The apparatus of claim 2 , wherein the logic is further configured to:

compare data representative of bits of the first vector and the second vector with bits of memory cells that store a truth table indicating results of the computational operation for various combinations of logic values, wherein the performing the computational operation is based at least in part on the comparison.

4. The apparatus of claim 1 , wherein the logic is further configured to:

receive an indication of the selected vector mapping scheme from the host device, wherein the selected vector mapping scheme is selected based at least in part on the indication.

5. The apparatus of claim 1 , wherein the logic is further configured to:

determine a quantity of elements of the first vector, a quantity of elements of the second vector, or both, wherein the selected vector mapping scheme is selected based on the quantity of elements of the first vector, the quantity of elements of the second vector, or both.

6. The apparatus of claim 1 , wherein the logic is further configured to:

determine a ratio of logic operations and arithmetic operations associated with the set of instructions, wherein the selected vector mapping scheme is selected based on the ratio of logic operations and arithmetic operations.

7. The apparatus of claim 1 , wherein writing further comprises the logic configured to:

write the data representative of the first vector to different sets of columns of the set of planes than the data representative of the second vector.

8. The apparatus of claim 1 , wherein writing further comprises the logic configured to:

write data representative of different sets of contiguous bits of an element of the first vector to different planes of the set of planes; and

write data representative of different sets of contiguous bits of an element of the second vector to the different planes of the set of planes.

9. The apparatus of claim 1 , wherein the set of planes is in a tile of the plurality of tiles, and wherein writing further comprises the logic configured to:

write, to a first plane of the set of planes in the tile, data representative of a first set of contiguous bits of an element of the first vector and data representative of a first set of contiguous bits of an element of the second vector; and

write, to a second plane of the set of planes in the tile, data representative of a second set of contiguous bits of the element of the first vector and data representative of a second set of contiguous bits of the element of the second vector.

10. The apparatus of claim 1 , wherein writing further comprises the logic configured to:

write, to a first plane of the set of planes in a first tile, data representative of a first set of contiguous bits of an element of the first vector and data representative of a first set of contiguous bits of an element of the second vector; and

write, to a second plane of the set of planes in a second tile, data representative of a second set of contiguous bits of the element of the first vector and data representative of a second set of contiguous bits of the element of the second vector.

11. The apparatus of claim 1 , wherein the logic is further configured to:

retrieve, based at least in part on the set of instructions, the first vector and the second vector from a memory coupled with the logic.

12. An apparatus, comprising:

a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and

logic coupled with the memory die and configured to:

receive, from a host device, signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;

write data representative of a first set of contiguous bits of at least one element of the plurality of elements to a first plane of a tile and data representative of a second set of contiguous bits of the at least one element to a second plane of the tile; and

perform, using associative processing, the computational operation based at least in part on writing the data representative of the first set of contiguous bits to the first plane and based at least in part on writing the data representative of the second set of contiguous bits to the second plane.

13. The apparatus of claim 12 , wherein the set of instructions indicates a second vector as a second operand for the computational operation, and wherein the logic is further configured to:

write data representative of a first set of contiguous bits of an element of the second vector to the first plane of the tile and data representative of a second set of contiguous bits of the element of the second vector to the second plane of the tile.

14. The apparatus of claim 12 , wherein the logic is further configured to:

write data representative of a first set of contiguous bits of a second element of the vector to the first plane of the tile and data representative of a second set of contiguous bits of the second element of the vector to the second plane of the tile.

15. The apparatus of claim 12 , wherein writing comprises the logic further configured to:

write the data representative of the first set of contiguous bits to a subset of columns of the first plane and the data representative of the second set of contiguous bits to a subset of columns of the second plane.

16. The apparatus of claim 12 , wherein writing is according to a vector mapping scheme, and wherein the logic is further configured to:

select the vector mapping scheme based at least in part on a quantity of the plurality of elements of the vector being greater than a quantity of rows per plane of the plurality of planes.

17. The apparatus of claim 12 , wherein writing is according to a vector mapping scheme, and wherein the logic is further configured to:

select the vector mapping scheme based at least in part on the set of instructions being associated with a ratio of arithmetic operations and logic operations that is greater than a threshold ratio.

18. The apparatus of claim 12 , wherein performing comprises the logic further configured to:

compare data representative of bits of the vector and bits of a second vector with bits of memory cells that store a truth table indicating results of the computational operation for various combinations of logic values; and

write data representative of a third vector that is a result of the computational operation to the plurality of planes based at least in part on the comparison.

19. An apparatus, comprising:

a memory die comprising a plurality of tiles each comprising a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and

logic coupled with the memory die and configured to:

receive, from a host device, signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;

write data representative of a first set of contiguous bits of at least one element of the plurality of elements to a first plane of a first tile and data representative of a second set of contiguous bits of the at least one element to a second plane of a second tile; and

perform, using associative processing, the computational operation based at least in part on writing the data representative of the first set of contiguous bits to the first plane and based at least in part on writing the data representative of the second set of contiguous bits to the second plane.

20. The apparatus of claim 19 , wherein the set of instructions indicates a second vector as a second operand for the computational operation, and wherein the logic is further configured to:

write data representative of a first set of contiguous bits of an element of the second vector to the first plane of the first tile and data representative of a second set of contiguous bits of the element of the second vector to the second plane of the second tile.

21. The apparatus of claim 19 , wherein the logic is further configured to:

write data representative of a first set of contiguous bits of a second element of the vector to the first plane of the first tile and data representative of a second set of contiguous bits of the second element to the second plane of the second tile.

22. The apparatus of claim 19 , wherein writing comprises the logic further configured to:

write the data representative of the first set of contiguous bits to a subset of columns of the first plane and the data representative of the second set of contiguous bits to a subset of columns of the second plane.

23. The apparatus of claim 19 , wherein writing is according to a vector mapping scheme, and wherein the logic is further configured to:

select the vector mapping scheme based at least in part on a quantity of the plurality of elements of the vector being greater than a quantity of rows per plane of the plurality of planes.

24. The apparatus of claim 19 , wherein writing is according to a vector mapping scheme, and wherein the logic is further configured to:

select the vector mapping scheme based at least in part on the set of instructions being associated with a ratio of arithmetic operations and logic operations that is greater than a threshold ratio.

25. The apparatus of claim 19 , wherein performing comprises the logic further configured to:

compare data representative of bits of the vector and bits of a second vector with bits of memory cells that store a truth table indicating results of the computational operation for various combinations of logic values; and

write data representative of a third vector that is a result of the computational operation to the plurality of planes based at least in part on the comparison.

26. An apparatus, comprising:

a host device configured to transmit signaling that indicates a set of instructions indicating a vector as an operand for a computational operation, the vector comprising a plurality of elements each having a respective bit length;

a device coupled with the host device and configured to perform associative processing, the device comprising a plurality of tiles that each comprise a plurality of planes, wherein each plane comprises a respective array of content-addressable memory cells; and

logic coupled with the device and configured to:

receive the signaling that indicates the set of instructions from the host device;

select between a first vector mapping scheme and a second vector mapping scheme for writing vectors to planes of the device;

write, based at least in part on the selected vector mapping scheme, data representative of a first set of contiguous bits of an element of the vector to a first plane and data representative of a second set of contiguous bits of the element to a second plane; and

perform, based at least in writing the data representative of the first and second sets of contiguous bits, the computational operation using associative processing.

27. The apparatus of claim 26 , wherein the logic is further configured to:

determine a ratio of arithmetic operations and logic operations associated with the set of instructions, a length of the vector based at least in part on the plurality of elements, or both, wherein the selected vector mapping scheme is selected based at least in part on the ratio, the length of the vector, or both.

28. The apparatus of claim 26 , wherein the set of instructions indicates a second vector as an operand for the computational operation, wherein the logic is further configured to:

write, based at least in part on the selected vector mapping scheme, data representative of a first set of contiguous bits of an element of the second vector to the first plane and data representative of a second set of contiguous bits of the element of the second vector to the second plane.

29. The apparatus of claim 26 , wherein the logic is further configured to:

write, based at least in part on the selected vector mapping scheme, data representative of a first set of contiguous bits of a second element of the vector to the first plane and data representative of a second set of contiguous bits of the second element of the vector to the second plane.

30. A method, comprising:

receiving, at an apparatus, signaling that indicates a set of instructions indicating a first vector and a second vector as operands for a computational operation;

selecting, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing; and

writing data representative of the first vector and data representative of the second vector to a set of planes each comprising an array of content-addressable memory cells based at least in part on the selected vector mapping scheme.

31. The method of claim 30 , further comprising:

receiving an indication of the selected vector mapping scheme from a host device, wherein the selected vector mapping scheme is selected based at least in part on the indication.

32. The method of claim 30 , further comprising:

determining a quantity of elements in the first vector, a quantity of elements in the second vector, or both, wherein the selected vector mapping scheme is selected based on the quantity of elements in the first vector, the quantity of elements in the second vector, or both.

33. The method of claim 30 , further comprising:

determining a ratio of logic operations and arithmetic operations associated with the set of instructions, wherein the selected vector mapping scheme is selected based on the ratio of logic operations and arithmetic operations.

34. The method of claim 30 , wherein the set of planes is in a tile, the method further comprising:

writing, to a first plane of the set of planes in the tile, data representative of a first set of contiguous bits of an element of the first vector and data representative of a first set of contiguous bits of an element of the second vector; and

writing to a second plane of the set of planes in the tile, data representative of a second set of contiguous bits of the element of the first vector and data representative of a second set of contiguous bits of the element of the second vector.

35. The method of claim 30 , the method further comprising:

writing, to a first plane of the set of planes in a first tile, data representative of a first set of contiguous bits of an element of the first vector and data representative of a first set of contiguous bits of an element of the second vector; and

writing, to a second plane of the set of planes in a second tile, data representative of a second set of contiguous bits of the element of the first vector and data representative of a second set of contiguous bits of the element of the second vector.